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LMC555: One short positive pulse before the rising edge

Part Number: LMC555

Hello, I am using the LMC555 to generate pulses with fixed duty cycle, 50% and 5Hz. The pulse is given to CPLD as clock. However it happens, although not frequently, that short (4us) before the rising edge of 555 output one positive pulse shows. The duration is approximately 100ns. This pulse triggers the flip-flops of cpld, generating wrong signals.

The circuit is all the same as in datasheet, except that only 100nF decoupling capacitor is used, where one extra 1uF elco is recommended. Could that possibly be the problem? Layout is designed as recommended. And since it only happens once in hours, and is critical, I would like to figure out the exact reason why this happens to be 100% sure that the circuit operates without problem for a very long time. If this short pulse cannot be eliminated then the other circuits will have troubles :(

Thank you!

  • Hi Shuo,

    Today is a holiday in the US, we'll get you a reply in the next couple days.

    Thank you for your patience!
    -Paul
  • Shuo,

    Is your schematic closer to figure 6 (section 8.4.2) or figure 17 (section 9.6) in the data sheet?
    Do you also have a bypass capacitor on CONT pin?

    Waveforms for pins 3, 2/6, and 5 would be helpful.
  • Hi Ronald,
    the circuit is the same in Figure 6, without capacitor on control pin. The control pin is left open.
    Yesterday we added a 1u MLCC on Vcc pin in one product, A, in which the false trigger happened 3,4 times without the cap. And we put a second product B nearby without mod. No false trigger is observed till now, for about 20 hours.
    It seems not all products behave the same, but the 1u cap helps to improve it. Not sure if the false trigger is completely gone... The test will run for days to see if the problem is solved. If it still happens I will then try a 10n on control pin. Since hundreds of products are already produced, fewer modifications the better...
    Thank you for your help!
  • Shuo,

    Noise is the likely cause. Does a a high power (noise) event occur close to the timing of the unwanted output pulse?
    This noise could be observed on the VCC pin or possibly the ground pin of the LMC555
    Just to be complete, what values were chosen for Ra, Rb, and C?
  • Hi Ronald,
    during the test the only high didt dudt part is the power supplies, which are far away from the digital parts. There are power and ground plane underneath and are connected to the timer though 1 or 2 vias. I haven't connected probes to vcc. There could be noise on vcc, which is not evitable since it's generated by buck converter.. The vcc of LMC 555 is filtered by a ferrite 600ohm @100MHz and 100n.
    The components used are 10k, 300k and 1u.
    Thank you!
  • Shou,

    The glitch output occurs just before the output going high normally. At that time output and discharge were low and timing cap voltage is falling slowly and very close to trigger threshold voltage. It seems unlikely that noise could trip both trigger and threshold comparators. It also seems unlikely that the trigger comparator could make output high then flop back. Because this glitch output is infrequent, I suspect a perfect random sync up between the time LMC555 triggers and some external signal that happens at the same time.

    Can you get waveforms of the glitch?

    I assume pin 4 is tied to pin 8. 10k, 300k and 1uF make 2.4Hz not 5 Hz. If you are getting 5Hz then the comparators are tripping very early.
  • Hello,
    year that makes sense, I will update the waveform at output next Monday. I probably recall the exact period or resistance wrongly, however it's several Hz. Thank you again for your help!
    Shuo
  • Hi Ronald,

    the waveform at LMC555 is channel 4, and chanel 1 is a false transition in CPLD, since the clock is falling edge triggered. What we observed is that the false trigger always happens shortly before the rising edge. Since it does rise up to 3V, I think the internal driver does try to drive the output high, but failed.

    New update on the test, it has been 4 days, the sample with additional 1uF MLCC on Vcc is still living, while the other is gone. It seems to be much more robust than before.

    Best regards

    Shuo

  • Shou,

    I replied twice this week and the post didn't show up, but it is working now.

    You are on the right track with the new capacitor. VCC noise is the key to this issue. The capacitor you added will help reduce noise so that the output is glitch free. I have studied the latch and output stage. The latch is cross coupled and have strong hysteresis for reliable output state changes. The output buffer is two stage for high gain.
  • Hi Ronald,

    thanks again for your help. Although not quite sure about the internal mechanismus why output behaved that way, however 1 uF more on Vcc does do the job.

    Always a good practice to follow the recommended value on datasheet.

    Best regards
    Shuo Cao