PLLATINUMSIM-SW: PLLATINUM SIM issue in Lock Time page

Derek,
To get straight to the answer, no.

This looks like you are using the LMX2572 with an output divider = 2.
PLLatinum Sim assumes the output divider is not changed.

Now you can't really model the time it takes to change the output divider; this is really just the time it takes to program it on the SPI bus.

So PLLatinum Sim should limit this to the bottom frequency of 1600 MHz (3200 MHz/2). But it looks like it is going all the way down the the bottom of VCO core 1, which is a little farther.

So for instance, suppose you wanted to measure the lock time from 1000 MHz to 3000 MHz. What this really means that the VCO is switching from 4000 MHz with divide of 4 to 6000 MHz with divide of 2. So the lock time would be the same as switching 2000 MHz to 3000 MHz with a divide of 2 all the time.

Regards,
Dean