LMX2595: Mismatch in critical noise model parameter and phase noise graphs

Farron,

The problem is that you are ignoring the VCO noise, and you cannot.
In figures 3 through 11, the VCO is contributing significant phase noise even in-band and even though it looks flat. If you were to try to simulate these results with our PLLatinum Sim tool and put in -228, your simulation would be way worse. If you put in -236 and account for the VCO noise, then it's spot on.

You have to use figure 24 that has a wider loop bandwidth. This is the measurement you should be using. Even for this, the loop bandwidth is not as wide as would be nice, but it is a better illustration.

The Wenzel oscillator is very low noise and not contributing at offsets above 1 kHz.

As it requires a super wide loop bandwidth to actually measure this -236 dBc/Hz number, we do not directly test in production, but from the few parts I have tried, it typically does not vary much,<1 dB.

Realize that the charge pump voltage only goes to 2.5 Volts, but we have got interest in a PLL only version of this device.

Regards,
Dean

Hi Dean:

Thanks for the prompt response, which I did not see till now due to the internet outage we've had all day here in North Dallas. 

OK, thanks for the warning on the VCO noise.   I had not noticed till you mention it that its 1/f corner is quite high compared to a discrete VCO--around 100kHz.  Let me see if I can reason out this high flat noise in the loop bandwidth and see what you think.  I could be wrong, but from the shapes of the closed loop noise, it looks to me that something else besides just high VCO noise is going on.  There IS enough frequency room for the loop suppression to be happening, but it is not, and the most likely culprit looks like Pn1Hz being a little high.    

1. The frequency we're considering VCO noise suppression in is about 20kHz to 200kHz, with an apparent loop bandwidth in the phase noise plots of about 200 kHz. 

2.  In this "inside the loop BW" frequency range we're almost in a 2nd order loop form where the phase error transfer function "H.e" as given in classic references applies.  This is a highpass function that shapes the VCO phase noise as referred to its input as a noise voltage that modulates noise onto the VCO output.   

3.  In the open loop state, the VCO input referred noise is flat on the 20dB/dec part of the phase noise curve, and is rising 10dB/decade as frequency drops below the VCO 1/f corner. 

4.  The H.e function is dropping 40dB/decade as frequency drops below natural frequency.  It gets from flat to 40dB/decade quite fast.  For example, if fn=200kHz, by 100kHz it is dropping 40dB/decade. I just tried a curve in Mathcad to confirm that, which is shown at the bottom.  

5.  So, in the closed loop state below the loop BW and below the 1/f corner of the VCO, which are almost coincident in the phase noise graphs, the input referred VCO noise Vncl is dropping 30 dB/decade as frequency goes down.  That comes from it rising 10dB/decade open loop, but being suppressed 40dB/decade by the loop. 

6.  By Sideband/Carrier = Ko*Vncl / Root(2)*f, phase noise on the VCO output is rotated 20dB/dec and is dropping 10dB/dec as frequency comes down inside the loop BW. That should get us down the 8 dB possible set by Pn1Hz = -236 by a frequency of about 25kHz, but we do not see that in the graphs.  We're not seeing any drop inside the loop BW, and we should be. 

7. Switching now as you suggest to Fig. 24, we see this in the wider loop (how wide not listed) as frequency descends below 1MHz H.e IS driving the noise down in the loop, bottoming out at about 400kHz at -111dB.  The predicted floor of Fig. 24 is -116, but we are firmly bottomed out at -111, 5 dB higher than we should be. 

7. H.e is plenty sharp enough to drive it the remaining 5 dB down in the frequency range available. So, something else STILL seems to be stopping the floor from getting quite all the way down.   With a Wenzel ovenized reference, though I don't know which one, it would not normally be the reference UNLESS the reference output were padded to bring up the floor.  Another possibility could be the 1/f noise in the PLL, though for it to be both flat from 400kHz down to 100kHz and then rise below that the 1/f would have to transition to a rise faster than just 1/f, which is not in keeping with the other phase noise graphs where it  seems pure 1/f down to 100Hz.  If not one of those two sources, the only one left would seem to be the normalized Pn1Hz..  If Pn1Hz of -231, not -236, that would explain perfectly what we see in Fig. 24.  

Just to confirm that, here is the calculation:

Pnflat = Pn1Hz + 20log(fout) -10log(Fpd) = -231 + 10log(14E9) - 10log(200E6) = -231 + 202.9 - 83.0 = -111.1, just as Fig. 24 shows. 

I don't know where I am making a mistake here.  It seems pretty clear that there is frequency room for H.e to do its filtering and suppress the VCO noise down further, but something is stopping it.  The shape in Fig 24 is correct, but then it is hitting a floor higher than it should.  In the large set of phase noise graphs, not even the shape is correct.  If the BW in those plots is the 200kHz it looks like, then down to 20kHz and acting over the 30dB/dec part of the VCO noise, there is frequency room to come down 10dB.   If Pn1Hz really is -236, then it should be able to come down about 8dB before hitting the floor at about 25kHz.  But, they are generally flat from about 200kHz down to about 20 or 10kHz. 

So, what do you think of the above analysis? I know you are using your sim tool, but these 5-8 dB kind of errors should be showing up in a hand calculation. 

If Texas Instruments were to offer a -236 PLL noise level in a part without the internal VCO and with a little higher charge pump voltage, I believe it would be a winner.  At this point I'm not aware of anybody else able to compete with that noise level.

This article series I am working on will be as follows:

Art. 1:  Review of PLL design and noise analysis methods.  Techniques from your book (I've been spending a lot of time in the 5th edition recently--great work) will be shown, with a few custom mods I have been working on.   It's getting long enough that it may end up being two articles. 

Art. 2 or 3:  Review of the lowest noise available parts, including synthesizers, VCO's, crystal references, op amps, and voltage regulators.  Several Texas Instruments parts will be featured. 

Art. 3 or 4:  Putting it all together in several examples, probably two with discrete VCO's and one with the LMX2595 for comparison of best of breed of these two forms.  This will review not just possible performance, but cost trade-offs also.  

If you had time to possibly review these, particularly the sections with modifications of your design methods and Texas Instruments parts, that would be greatly appreciated.  If so, just ping me at farron.dacus@longwingtech.com with your current e-mail, and as they become available I will send you the drafts. 

Thanks,

Farron

Shape of H.e(s), with damping factor of 0.7 and natural frequency of 200kHz. As you can see, it transitions to 40dB/dec quite quickly.  

Hello Again, Dean:

Sorry for all the trouble it is to hash through these details.  We're getting close to -236, maybe just slightly off as in about -234 in the reference doubler case, as follows. 

I'll check out PLLatinum Sim, but right now I can't really accurately use it for this particular issue because the details of the circuitry used to take the noise graphs are not given in the datasheet.  I don't even really know the bandwidth, though for most of the noise plots it looks like about 200kHz. 

But, we can check the numbers you provided using the sim with a reasonable estimate of transfer function.  

For Figure 11 at 8 GHz and 100kHz offset, we have these simulated and calculated numbers to compare:

1.  Simulated PLLflat = -119.2 and calculated = -120.9.  We're off by 1.7dB, though this is mostly explained by being close to the bandwidth and not having the closed loop transfer function to calculate with.  

2.  Simulated PLL1/f = -119.8 and calculated = -120.9 (a coincidence), off by 1.1dB. 

3. Simulated VCO noise closed loop at 100kHz offset = -118.5.  Without the exact functions I cannot calculate it, but the free running is about -108, some coming in from about 200kHz to 100kHz dropping 10.5 dB does seem about right, as we are not down to 12dB per octave on loop noise suppression till about 100kHz. 

Put the calculations together with your simmed VCO noise and the total is -116.7, with the noise graph showing -113.4, a difference of 3.3dB.  You reported above that 1dB of this is that use of the reference doubler degrades Pn1Hz from -236 to -235.  The remaining difference is 2.3dB. 

Now while I don't have the exact transfer functions, if I model it as second order with natural frequency of 200kHz and damping factor of 0.7, then at 100kHz there is a peaking in the closed loop function of 1.5dB.  That reduces the 2.3dB to 0.8dB, so that finally takes it down to an acceptable error.  It seems like we're in agreement, except that in the case of using the reference doubler the PLL flat noise may be closer to -234 instead of -235.  

What led me to the concern of high Pn1Hz are the unexpectedly high 1/f corners of both the PLL noise and the VCO noise.  Engineers using better VCO modules are used to 1/f VCO corners of just a few kHz.  But here we have 1/f noises of both PLL and VCO that in a logarithmic sense apply over most of the 200kHz bandwidth in the noise plots.  At 10dB/decade each, these rotate what should be 20dB/dec noise suppression in the bandwidth to be flat, so it looks just like a higher Pn1Hz. Then, the 1/f corner relative to that higher flat noise looks like about 10kHz (a logical number) rather than the 50kHz  to 100kHz that it really is, adding to the confusion.  It might be worthwhile putting a short paragraph about that in the datasheet, as well as the details of the loop BW's in use, maybe even the exact circuitry and/or transfer functions for engineers that really dig into it.   

I might mention there are few bugs, unclear points, and possible improvements in the datasheet you might consider:

1.  As concluded above, it may be that the Pn1Hz with the reference doubler is closer to -234.  That seems to be the case in Fig. 24 also.

2.  In my opinion, engineers performing noise analysis need the details on the loop design and reference used with the noise plots.  I note that with the Wenzel 501-04623G, the frequency where the reference noise asserts a 1dB rise in phase noise is about 250Hz, and it is becoming dominant at about 100Hz.  A short discussion on delta sigma order used might be good if this has a noticeable effect.

3.  Any variation in the noise parameters as a function of charge pump current would be good to know.  Sometimes a designer will want to compensate for changes in VCO gain by altering charge pump current, in which case he needs noise parameters for less than max current.  Is that built into PLLatium Sim?

4. The spec on charge pump current from 3 to 15mA says this is the SUM of the up and down current--a way of reporting this spec I have not seen before.  If that were true it would be divided in half for design calculations.  Perhaps that was meant to be the average of up and down current.  Anyway, that's an important one to be clear on. 

5.  Fig 8 says Fout/2 when it should be Fout/4. 

In my article I will be dealing with these noise effects for the LMX2595, so the word will somewhat get out that way.  I'll make a point to use PLLatinum Sim for noise predictions in the article, in addition to my normal analysis.  If there is key information in PLLatinum Sim that is not in the datasheets, I can mention that. 

Thanks for the detailed help...

Farron

 

Dean, I don't see that Excel file you mentioned. It is not under the "Files" button above, which was last posted to in June 2016. Am I just missing it, or is it not attached? Farron.

Thanks Dean--that looks like quite an Excel file.

Did you see the longer reply just above the file request? I had concluded we are converging, but it looks like PN1Hz is closer to -234 than -235 with the reference doubler on.  There were a few questions up there if you can stand to spend any more time on this.

I downloaded PLLatinum Sim and am giving it a test drive.  Quite nice looking and apparently very easy to use, but it has some unclear behavior and raises some questions:

1.  Is there a user guide?  I don't find one on the TI site, in a wider on-line search, or in the form of any instructional videos on YouTube.  If there is no guide, perhaps you might expand your short intro in the 5th edition when you write the 6th edition.

2.  To get noise profiles matching the datasheet takes quite high phase margins, about 70 degrees.  Is that the norm using this part?

3.  It won't take loop BW's above about 700kHz. At first I thought this was because it would not take C2 below 2700pF when finding C2 itself, but it will allow C2 to be forced below that.  But, then it won't get good phase margin.  For example, ask for 50 degrees and it gives you 10 degrees.  Is that because of an RC filter on the die VCO input that limits BW? In any event, there seems to be something a bit odd there that I would need to explain to readers in the article, either a bug or more likely simply something I don't understand.  If you want to get in as a coauthor on this and make sure I don't tell it wrong, that would be welcome.  

4.  In auto mode, it sure wants to space out the R3-C3 pole.  The LMX2595 EVM instructions schematic REALLY spaces out the poles also, all the way to about 5 or 6 MHz.  That seems to be begging for high spurs, but PLLatinum Sim apparently does not show any below -100dBc.  I'm not seeing any spurs at all in that down to -100dBc range--is that for real?

Best,

Farron

Hello Dean:

Thanks for the detailed responses, and for the informative report.   

I must be wearing out the time you can give one forum user, so I'll try to wrap it up for the present (though I'll almost certainly have to come back later). 

But, I do have one key question.  Getting these high phase margins to prevent noise peaking is necessarily reducing filtering of spurs.  Are the resulting spurs with those high phase margins generally working out for demanding applications like cellular base stations?

Best,

Farron