LMK04610: Power-up time

Mark Guastaferro

Part Number: LMK04610
Other Parts Discussed in Thread: LMX2592, LMX2594

Looking at using the LMK04610 with PLL1 bypassed. How long does it take the device to power-up from reset? In this case I am assuming the time from when the SPI registers have been programmed to when the PLL are locked with outputs ON.

To save power, we would like to power-down the LMK04610 when it is not needed, which is the reason for the power-up time question. As an alternative, could we use SPI commands to power down as many sections of the device as possible to minimize power consumption, but allow a speedier turn-on recovery time? If so, is there any information on a trade-off between possible standby power modes and turn-on time?

over 5 years ago

0 Timothy T over 5 years ago

TI__Mastermind 28530 points

Hello Mark,

I can try to give you some rough guidelines.... When you talk about trade-offs between power and turn-on time. What orders of magnitudes are you looking at / even make sense for you to be concerned about?

Mark Guastaferro said:
could we use SPI commands to power down as many sections of the device as possible to minimize power consumption, but allow a speedier turn-on recovery time?

Should be, for example you could power down all the outputs, then for bringup - power up all the outputs and do a SYNC (if required). This would be faster for number of registers programmed and not needing to wait for PLL2 to lock. Take a look at the current consumption section of the datasheet for a idea of possible savings. Without knowing your configuration I can't really say the benefit... for example, if you have only 2x HSDS 4 mA outputs, that's significantly different power than 10x HCSL.

Mark Guastaferro said:
In this case I am assuming the time from when the SPI registers have been programmed to when the PLL are locked with outputs ON.

Are you going to program the device at the max SPI bus rate of 20 MHz? If not, what rate?

For total bringup time to locked, we're looking at...

1) Ramp-up time of power supply to final supply voltage.

2) Time for setting RESETN low, 1 --> 0 (25 ns) --> 1.

3) Time to program all registers, using streaming (one address write and repeated data writes) 88.1 us @ 20 MHz.

4) Set DEV_STARTUP = 1; (1.3 us) @ 20 MHz.

5) Wait for lock & clock outputs.... this will depend on calibration time & PLL loop bandwidth.

> Can you advise the OSCin frequency and the PLL2 loop bandwidth? I think this #5 item is the primary focus of your question based on your quoted comment above?

73,
Timothy

0 Mark Guastaferro over 5 years ago in reply to Timothy T

TI__Genius 11095 points

Hi Timothy,

Thanks for the information and details. The clocking system is still in design, so there is some flexibility in the possible configurations. The OSC input will be 100 MHz from a very clean source in order to avoid using PLL1 as a jitter cleaner. PLL2 bandwidth will preferably be set to optimize output jitter. One of the outputs will be used to be the reference clock for an LMX2592 PLL. There will be three other outputs, not sure of their mode or drive levels yet.

The goal would be to have a turn-on time from a low power state in 100 usec or so, assuming the device had been on at some previous time and registers had been programmed at that time. I had run a power-up test on the LMX2594 using its POWERDOWN register bit and the response time was over 2.5 msec, which is too long. I think most of this was for internal LDOs to power up. My concern is the LMK06410 response might be similar to this from a full power down. The assumption is that a way around this is to keep some parts of the clocking devices powered up to avoid the very long power-up events (such as an LDO) and then the primary turn-on delay comes from minimal register writes and PLL lock times. External supplies would not be ramped down.

SPI writing will probably be at max speed.

0 Timothy T over 5 years ago in reply to Mark Guastaferro

TI__Mastermind 28530 points

Later this week I expect I can measure the basic EVM case locktime, this will give an idea of trade-off. I'll post the results here.

73,
Timothy

0 Timothy T over 5 years ago in reply to Timothy T

TI__Mastermind 28530 points

Hello Mark,

Without doing anything special, I'm getting lock times in the 10 to 15 ms range from the moment send the DEV_STARTUP = 1 command.

I used a 100 MHz reference via CLKin1 direct to PLL2. I measured a 1 GHz output.

73,
Timothy

0 Mark Guastaferro over 5 years ago in reply to Timothy T

TI__Genius 11095 points

Thanks, Timothy
This start-up time is longer than we hoped. I may contact you offline to discuss options.

Clock & timing

Clock & timing forum

LMK04610: Power-up time