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CDCM6208: CDCM6208 I2C connection problem

Part Number: CDCM6208

Hello,

My customer has I2C communication problem of CDCM6208 on already released product. The device intermittently (about 1/200) fails to accept initial setting.

The system writes the setting from register 0 to 20, and hangs up after regisiter3 write because CDCM6208 hold “NAK” signal. This hang up always happen for register 3 access when the problem happen. And the problem cannot be observed if the customer changes the register writing order (for example Regster3 -> Regster0 -> Register1 ….)

 

Have you ever experienced this kind of problem? Or the device have access limitation potentially?

 

Best regards,

Tetsuro

  • Hi Tetsuro,

    One possible cause for the issue is noise on the I2C lines. For example, a power plane located above/below the I2C traces can couple noise onto the I2C lines. In this situation, one could add a small capacitance on the I2C bus (less than 100pF).

    Kind regards,
    Lane
  • Hello Lane,

    I found that hold time between SDA and SCL of the customer application was 200ns. But satandard mode need 300ns(min). Probably this will cause the issue. By the way could you explain me reason why the specification says 0ns and 300ns is just commented? In additon, 0ns is OK for fast mode?

    Best regards,
    Tetsuro
  • Hi Tetsuro,

    This wording was adapted from the I2C Bus Specification. Hold time of 300ns will ensure that SDA is stable when sampled as long as the SCL. Value of 300ns was selected as that is the SCL maximum fall time spec.

    0ns hold time means that data may be improperly sampled if the SDA is unstable after SCL falling edge. You should be fine with hold time > 0ns for fast mode.

    Kind regards,
    Lane