CDCM6208: Whether other outputs are affected when changing the frequency of an output

Shinichi Inoue

Guru 19651 points

Part Number: CDCM6208

Dear Specialists,

My customer is considering CDCM6208 and has a question.

I would be grateful if you could advise.

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I am considering using CDCM6208 as CLK input to K2H and FPGA.

I'd like to change y1(FPGA) while supplying y0(K2H).

If y0 is not changed from the default 100 MHz and y1 is changed from the default 100 MHz to 125 MHz, the register is changed via I2C.

In this case if y1 is rewritten, is y0 affected?

Or may we consider that y0 is not affected and even though y1 is changed?

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I appreciate your great help in advance.

Best regards,

Shinichi

over 5 years ago

0 Shawn Han over 5 years ago

TI__Genius 9920 points

Hi Shinichi,

From CDCM6208 block diagram, Y0 and Y1 share one output clock divider, so when Y0 and Y1 are enabled, they will output the same frequency.

Y0, Y1 share one output divider.

Y2, Y3 share one output divider.

From Y4 to Y7, each port has an individual output divider.

You can change frequency in other output port with different divider.

Best Regards,

Shawn

0 Shinichi Inoue over 5 years ago in reply to Shawn Han

Guru 19651 points

Hi Shawn,

Thank you for your reply.

I'll share your information with the customer and make him consider to change output port.

I appreciate your great help.

Best regards,
Shinichi

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CDCM6208: Whether other outputs are affected when changing the frequency of an output