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LMK04208: LMK04208

Part Number: LMK04208

Hi

We are using the follow config to run the LMK with local VCXO

We want to use clk_in0  as reference and sync to the LMK output

We tried to change the config but without any success. what are we missing? 

The current config: 

R0 (INIT) 0x00160040
R0 0x00140300
R1 0x00140301
R2 0x00140062
R3 0x80140603
R4 0x00140304
R5 0x80140185
R6 0x01100006
R7 0x01300007
R8 0x04010008
R9 0x55555549
R10 0x9102410A
R11 0x0401100B
R12 0x1B0C006C
R13 0x2302826D
R14 0x0200000E
R15 0x8000800F
R16 0xC1550410
R24 0x00000058
R25 0x02C9C419
R26 0xAFA8001A
R27 0x10001E1B
R28 0x00201E1C
R29 0x0180019D
R30 0x0200019E
R31 0x003F001F

Thanks

Oded

  • Hi Oded,

    Attached is the TICS Pro configuration file based on your register setting. 

    Open TICS Pro --> Select Device --> Clock Generator/Jitter Cleaner (Dual loop) --> LMX04280.

    File --> Load --> (select the attached .tcs file).

    On the left column, select CLKins and PLLs. On the right you will see the block diagram and frequency planning.

    As you can see, your register setting has selected CLKin1 as the reference clock for PLL1. If, in your board, you don't have anything in CLKin1, PLL1 will not lock. Please try play around TICS Pro and setup your configuration. you can export the register setting if you select Raw Registers on the left column.

    4208.tcs

  • Dear Noel,

    Thank you for your quick answer

    We have retest the issue and better understanding the problem. 

    At our design we got two boards (each with LMK) which work in un-synchronize mode. At one point the first card become master and the second to slave (where the LMX should be sync to CLK_in0, which is output of the first LMK, please see attach scheme). The clk_in0 is signal ended clk with 0.1uF cap to clk_ino_N and 50ohm termination and 0.1uF serial cap to clk_in0_p. Attach the clk input image

    The input define as bipolar

    As it look when we move to slave mode and change the initial config (as seen in the first post) to clk_ino:

    80140603

    2302806D

    The slave LMX do not lock with clk_in_0 (even that there is good clock at this input). 

    Only after few time that we added capacitance element to this enter  (Scope prob) the LMX lock in with this input

    It there way or register to push the LMX to lock to the input clk

    Thanks

  • Hi Oded,

    You are connecting a LVPECL output to CLKin0 of another LMK device. 

    Then, you should add a termination load at CLKin0 as follows.

    In addition, make sure the first LMK device is still locked when you are using the second LMK device.