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LMK04805: slow frequency swinging +-1..10Hz

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Replies: 3

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Part Number: LMK04805

We are using the LMK04805 with a CVHD950 122.88MHz VCXO and a 30.72MHz TCXO, then we set the output divider of clock out 0 to 1, so we have 2293.76MHz at the output. Phase noise looks ok above 10Hz. But on the spectrum analyzer we can see some very slow jumps or swings of with a frequency of less than +-1..10Hz and a period of 0.1..1s. We also take the reference instead of the TCXO from an Anritsu MG3692B with the same 30.72MHz and can't see a difference. If we set the Anritsu to 2293.76MHz and connect it to the spec, it is, as expected, without any swinging. I have attached the TICS file of our settings. Any ideas?

lmk04805_driverinit_190523.zip

  • 1, In spectrum, is it frequency jump or amplitude jump? Can you use cell phone to capture videos to share in E2E?
    2, LMK04805 PLL1 and PLL2 are locked, right? How about loop filter bandwidth and phase margin? It can be simulated by "Clock Design Tool" www.ti.com/.../CLOCKDESIGNTOOL

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • In reply to Shawn Han:

    I have checked with 1Hz 3° and 24Hz 45° PLL1 loopfilter, bis changing PFD frequency. Please see videos, pictures, schematic, tics and PLLattinium files in the attached zip. We get rid of the swinging by using the anritsu as reference an choose 24Hz 45° loopfilter. But there are some spurious.

    But how can I improve it with my TCXO? If I switch to 24Hz the low frequency phase noise is bad. I would not expect that bad values from the T604-030.72M TCXO? Can you check our schematic in the zip file?

  • In reply to Andreas Zutter47:

    The frequency shift is caused by unstable loop. Make sure phase margin > = 45° (for example, 45°, 55° or 75° etc.)
    For loop bandwidth, LMK04805 can support LBW >= 10 Hz.
    Datasheet shows "PLL1 typically uses a narrow loop
    bandwidth (10 Hz to 200 Hz) to retain the frequency accuracy of the reference clock input signal while at the
    same time suppressing the higher offset frequency phase noise that the reference clock may have accumulated
    along its path or from other circuits."

    Trade off low frequency offset phase noise, we have to try the PLL1 LBW in 10~24 Hz.
    or consider how to improve phase noise from TCXO.

    ____________________________________________________________________________________

    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

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