LMK04610: Willing to check my configuration file?

Hi Jeff,

Conceptually, there's two use cases where a jitter cleaner cascaded PLL shines:

1. When the input reference has low frequency error but high jitter (a 'dirty' signal)
2. When frequency multiplication is required, because the GCD between the available reference and the desired reference is very small (e.g. 122.88 MHz and 100 MHz can be compared at 160 kHz)

If your 100 MHz signal is very clean, the frequency is high enough that there may not be a good reason to use PLL1. On the other hand, if the far-out reference noise is poor, then PLL1 can be used to substitute the far-out phase noise performance of the VCXO.

Next, it is important to know the integration bandwidth for your application. For example, high speed ADC clocks may require clean jitter at very high offsets, but if the data is processed using FFT, the integration bandwidth may not extend below the bin size. On the other hand, audio ADC clocks have generally lower bandwidth, but meaningful data exists down to 20 Hz limits. And the integration bandwidth may impose requirements on the loop bandwidth. So:

• What are you clocking?
• What is the integration bandwidth for the jitter? (i.e. where do you care about potential frequency errors?) Is the application driven by bit error rate?
• What is the acceptable jitter for your application? ("As low as possible" can drive needlessly expensive design decisions; in many cases, there is "good enough")

For picking an appropriate loop bandwidth, I refer you to the following documentation: https://e2e.ti.com/support/clock-and-timing/m/videos__files/664163

As far as configuring the LMK04610, I note the following:

• Outputs 7/8 are configured for 200MHz, but output 7 appears to be powered down.
• Set CLKINx_EN on the same clock directed by SW_REFINSEL.
• If you care about LOS detection, OSCIN_BUF_LOS_EN must be set.
• Unless lock time is a critical parameter for your application, I would leave the settings at the defaults.
• Once you pick a loop bandwidth for PLL1 and PLL2, the TICS Pro tools will handle determining the loop filter settings.
• The VCXO ppm/V can be converted to kHz/V by noting that 1ppm on 100MHz is 0.1kHz; so 8ppm/V = 0.8kHz/V, and 4.5ppm/V = 0.45kHz/V.

Putting not too fine a point on it, the TICS Pro for the LMK04610 has a bewildering number of controls, very few of them need to be adjusted in most cases, and it is much easier to correct errant settings within a desired configuration than to specify a priori what each setting ought to be.

Regards,

I forgot to attach this file in my previous post.

Thanks, Jeff

Derek,

I don't see the post I thought I had submitted last week.

I plan to use the LMK04610 to create a low jitter (80-100fs RMS) 200MHz sample clock for an ADC and several other 100MHz clocks.  The Bluetooth IF signal being sampled has 80MHz bandwidth and is centered at 140MHz.  That we're using an FFT does not help us.  The jitter requirement applies to the entire 80MHz bandwidth.  So what range should the phase noise be integrated over?

Is the jitter cleaning approach that uses both PLLs appropriate?

I've studied the presentation about selecting the appropriate loop bandwidth, but am still struggling.  I've attached phase noise plots of the TCXO and VCXO I plan to use.  For the PLL loop bandwidth, don't I need to know both the PLL's phase noise pedestal inside its loop bandwidth and my VCXO phase noise versus offset frequency (which I have) to set the loop bandwidth?  Where is the PLL1 phase noise versus offset frequency information?

For the PLL2 loop bandwidth, don't I need both PLL2's phase noise and PLL2's VCO's phase noise versus offset frequency to select PLL2's loop bandwidth?  Where is this information?

Thanks, JeffJitter Cleaners.zip