• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 20 subscribers
  • Views 335 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2571: I2S input at 192k/16bit

Gareth P
Prodigy 50 points
Part Number: LMX2571

Hi Noel

I am looking at using the LMX2571 in an FM broadcast application, modulating frequency range will be 30Hz - 57KHz.

Will the 2571 support a modulating frequency of 57KHz providing the loop filter is wide enough?  I guess it probably comes down to: will the 2571 support an I2S stream at a sample rate of 192k/16bit (at least 3.072MHz clock rate).

My next question, if the above is supported, is there any way to feed I2S directly into the I2S/FSK pins without having a microcontroller in between to do a conversion on the frame sync pulse?  The reason I ask is because the timing diagram in datasheet for the I2S FSK input indicates that the frame sync pulse needs to coincide with the first bit clock, where at the Philips I2S specification indicates that this frame sync bit precedes the first bit clock.

One more question, the 2571 datasheet indicates that toggling the SPI pins while the PLL is in lock may degrade the phase noise, so I have decided not to use FSK FAST mode over SPI.  Can you confirm if the same is true when toggling the FSK pins in I2S mode?

Thanks for your help

Gareth

  • 0
    TI__Guru* 81490 points

    Hi Gareth,

    The I2S sample clock rate could be 3.072MHz or higher. We have seen from customers and we have also tried even with a much higher clock rate. 

    One of the reasons why the I2S data comes from a MCU is because the information that is embedded in the data steam is not an I2S-formated audio. In other words, it will not work if you feed the I2S data, from an audio codec, to LMX2571 directly.

    regarding the frame sync signal, it has to be either high or low (user configurable) before the first CLK comes in. It has the same timing specification as the SPI interface. 

    Phase noise degradation means some sort of spikes due to crosstalk when we toggling the SPI. I believe the spikes might be there too when we toggling the I2S interface because this is due to crosstalk. However, I do not think the spikes is an issue as we are modulating the PLL, the modulation depth is much higher from the modulation than it is from the spikes.

  • 0 in reply to Noel Fung
    Prodigy 50 points

    Hi Noel

    Thanks for this, very much appreciated.