• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 3 answers
  • Subscribers 20 subscribers
  • Views 565 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMK04821: LMK04821

sumathi m
Intellectual 855 points
Part Number: LMK04821
Other Parts Discussed in Thread: LMK04616, LMK04610, LMK04828, AFE7686, CDCM6208

Hello,

We are using LMK04821 in one of the enodeB design.

Currently the reference input of 122.88MHz is applied to CLKIN0.

We have provided option for external clock of 10MHz/ 30.72MHz for CLKIN1 input.

The JESD204B clocks used are 245.76MHz on DCLK, and 120KHZ on SDCLK with input clock of 122.88MHz.

Pls could you let me know whether it is possible to generate JESD204B clocks used are 245.76MHz on DCLK, and 120KHZ on SDCLK with input clock of 10MHz or 30.72MHZ external clock.

Regards,

Sumathi

  • 0
    TI__Mastermind 28960 points

    Hello Sumathi,

    The maximum SYSREF divide is 8191. The minimum VCO frequency is 1930 MHz. 1930/8191 = about 0.236. It is not possible to generate 120 kHz output using LMK04821 internal VCO. You could use an external 245.76 (or 491.52, or 737.28) MHz VCO/VCXO with PLL2 and return the output of this external oscillator to CLKin1 through the FB_MUX input. Then, feed the 122.88 MHz reference input directly to OSCin instead of CLKin0. While this configuration bypasses the jitter cleaning PLL1, it still uses a presumably high quality VCO/VCXO to clean the input reference in PLL2.

    Regards,

  • 0 in reply to Derek Payne
    Intellectual 855 points

    Hello Derek,

    Thanks for the support.

    we are using LMK04821 in out circuit. it is already working with 122.88MHz for 245.76MHz and 120KHz.

    The enodeB has option for 10MHz / 30.72MHz external clock input option. So it is required to test the LK04821 with external clock of 10MHz / 30.72MHz.

    We tried to do the setting in TICS pro , but not able to get the output clocks.

    The observation is the output clock is ok with 122.88MHz. 

    The query is whether it is possible to generate 245.76MHz and 120KHz with external clocks.

    Regards,

    Sumathi

  • 0 in reply to sumathi m
    TI__Mastermind 28960 points

    Sumathi,

    The only way I could think of doing it with LMK04821 is by providing 245.76 MHz or 491.52 MHz to CLKin1 somehow. This could be done by using PLL1 to generate 245.76 MHz or 491.52 MHz from an external VCXO, then feeding this input into CLKin1 instead of OSCin and use distribution mode in the VCO_MUX to fanout the signal. 120 kHz could be generated using the SYSREF divider at 2048 or 4096 respectively. Then, by using the FB_MUX with one of the DCLK outputs and switching PLL1 NCLK mux to the FB_MUX input, PLL2 could be bypassed entirely.

    There are other ICs which may be better choices for this specific frequency combination. Take a look at the LMK04610 or the LMK04616, which have a much more flexible 16-bit channel divider and can support generation of 120 kHz while still operating as a cascaded jitter cleaner PLL.

    Regards,

  • 0 in reply to Derek Payne
    Intellectual 855 points

    Hi Derek,

    Thanks for the support.

    Initially we were using LMK04828 as per AFE7500 / AFE7686 EVM.

    since it is required that sysref frequency must be 120KHz and LMK04828 does not support 120KHZ, we were suggested to use LK04821. please refer the below link

    . we have already changed the IC from LMK04828 to LMK04821 and the board design is done.

    Now we require the register settings to generate the DCLKOUT clock of 245.76MH, 122.88MHz, and sysref of 120KHz with external input of 10MHz or 30.72HZ to clockIN1.

    The CLKNIN0 is fed with 122.88MHZ as input from an another clock generator CDCM6208 (same as K2L EVM). For external clock option, SMA connectors are provided for CLKIN1.

    Hope the requirement is clear.

    From the link, it seems that 245.76MH, 122.88MHz, and sysref of 120KHz generation is possible with LMK04821. Please let me know if you are seeing any issues?LMK04821_SYSREF_120kHz_setting_for_TICS_Pro.tcs

    Regards,

    Sumathi

  • 0 in reply to sumathi m
    TI__Mastermind 28960 points

    Hi Sumathi,

    Thank you for linking me to Shawn's answer, I had completely neglected the VCO post-divider on LMK04821. I see that it should be possible with VCO = 2949.12 MHz, post-divide = 4, channel divide = 3 (to generate 245.76 MHz) or 6 (to generate 122.88 MHz) and SYSREF divide = 6144 (to generate 120 kHz). I see no problems with this configuration, and I apologize for taking so long to recognize it.

    If the R-divider for CLKin1 can be reprogrammed during operation, it is possible to support input clock frequencies of both 30.72 MHz and 10 MHz. Assuming a 122.88 MHz VCXO and a constant phase detector frequency of 80 kHz:

    • For 30.72 MHz, R=384, N=1536
    • For 10 MHz, R=125, N=1536

    If the N-divider for PLL1 can be reprogrammed during operation, since 30.72 MHz is a multiple of 122.88 MHz, the phase detector frequency can optionally be increased in this case, up to 30.72 MHz (R=1, N=4).

    Regards,