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CDCM6208: CLK drop

Part Number: CDCM6208

Hi Sirs,

Sorry to bother you.

Currently using TI's CDCM6208 clock gen.

However, it is found that port 5 provides 100MHz to USB3.0. When some boards are turned on, it will remain at around 99MHZ; when it is turned on halfway, the frequency will drop and it will not be able to recover 99MHZ

We would like to know if the frequency of the clock is not correct, have any suggestions?

  • What do you mean by "it is turned on halfway" ?

    When it is turned on halfway, were the registers programmed correctly? I recommend to compare the register readback between the good startup and halfway startup.

    If the frequency is incorrect and you have confirmed that the device is programmed correctly, you might try to calibrate the VCO by following datasheet section 8.3.3 .

    Kind regards,
    Lane