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LMK04208: Changing the VCXO and reference on ZCU111 to 125MHz and 10Mhz to generate 125MHz clock produces a drift of +30PPM

Meera Balakrishnan
Prodigy 20 points
Part Number: LMK04208

I'm working with the ZCU111 Board to generate a 125Mhz clock.  The board came with a VCXO of 122.88Mhz and a 12.8Mhz reference.  ZCU111 was modified to use 125Mhz (50 ppm)  as VCXO and was provided a 10Mhz reference (100 ppb) at CLKin0. The LMK04208 is used as a jitter cleaner with the 10Mhz reference and the VCXO for jitter cleaning.  The register configurations were generated using the TICS Pro tool v1.6.10.0.  I have pasted the values below.  The tool showed 125Mhz. 

However, with a frequency counter, clock output measured at CLKout2 is 125MHz, with a +30 PPM.  Is there any guidance you can provide on programming the LMK04208 to get the actual 125MHz without so much drift?

R0 (INIT)    0x00160040
R0    0x00143200
R1    0x00143201
R2    0x00140302
R3    0x40140023
R4    0x40140024
R5    0x80141E05
R6    0x01100006
R7    0x01100007
R8    0x06010008
R9    0x55555549
R10    0x9102410A
R11    0x0401100B
R12    0x1B0C006C
R13    0x2302806D
R14    0x0200000E
R15    0x8000800F
R16    0xC1550410
R24    0x00000058
R25    0x02C9C419
R26    0xAFA8001A
R27    0x1000179B
R28    0x004125DC
R29    0x0100031D
R30    0x0200031E
R31    0x003F001F

  • 0
    TI__Mastermind 28960 points

    Hello Meera,

    Once a PLL is locked, mathematically there should not be any constant frequency error between the reference frequency and the feedback frequency.

    1. Are you sure that your frequency counter is using the same frequency reference as the source generating the 10 MHz? The choice of input frequency is fortuitous, since it should be possible to feed the 10 MHz signal directly into the frequency counter external reference port. 
    2. Are you sure the PLL is locked, and is remaining locked for the entire duration of the test? You can check this by routing the PLL1 & PLL2 DLD signal to the LD_MUX and probing the line during the test to observe any changes in state. Alternately, the PLL_R/2 and PLL_N/2 signals can be brought out on the LD_MUX and HOLDOVER_MUX pins to look for any low-frequency oscillations that may be impacting output frequency accuracy without strictly violating phase lock.

    I will examine the register programming once you can confirm both of the conditions above are true.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 20 points

    Hi Derek,

    Thank you for your reply. 

    Let me answer your # 2 first.

    1. PLL1 & PLL2 DLD were routed to an LED on the ZCU111 board and they remained locked for the duration of the test.
    2. It turns out that the signal from the 10Mhz crystal was the issue.  I swapped the 10Mhz (100ppb) crystal with the 12.8Mhz (30ppb) that was provided on the ZCU111 board.  Now, with the 125Mhz VCXO and a new configuration file for the registers (to account for the change in the Clkin0 frequency), i was able to generate 125MHz at Clkout2 with less than 1 ppm drift.

    Thank you again,

    Meera