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LMK00301: Can recommend a 156.25M clock ultra-low additional jitter buffer chip?

Part Number: LMK00301
Other Parts Discussed in Thread: CDCLVP1204, LMK00334

Hi

Can recommend a 156.25M clock ultra-low additional jitter buffer chip,

a little less than the lmk00301 channels, smaller size, the jitter is preferably as small as 50fs.

Thanks

  • Can I recommend a 156.25M clock ultra-low jitter jitter chip, of which 156.25 is a differential clock;
    Less than the number of lmk00301, the volume is smaller, and the jitter is preferably as small as 50fs;
    The number of buffer channels can be 1:2 to 1:4.

  • Consider LMK00334 or CDCLVP1204

    Kind regards,
    Lane

  • Hi Lane

    Thanks for your advice.

    The jitter of the CDCLVP1204 is smaller, but does not support the HCSL level;
    Can recommend a little less than the lmk00301 channel number, smaller size, jitter less than 50fs, support HCSL level buffer
    Or please tell us how to use CDCLVP1204 to convert, the output LVPECL is converted to HCSL, the input HCSL is converted to the level supported by CDCLVP1204, and the jitter is generally increased.
    Thanks a lot.
    Beat Regads
    Elsa Duan
  • Hi Elsa,

    For the HCSL input to CDCLVP1204: Place a 50-ohm termination to GND at the end of the controlled impedance transmission line. After the 50-ohms, use and AC-coupling capacitor and resistor divider to set the DC bias on both lines. You can use Rtop = 8.7K and Rbottom = 5K with VCC = 3.3V to set the bias to 1.2V .

    For the CDCLVP1204 output converted to HCSL: Place a 150-ohm termination to GND on the driver outputs for biasing. Use a 8-ohm series resistor before the transmission line for biasing. After the transmission line, use an AC-coupling capacitor and resistor divider to set the DC bias on both lines. You can use Rtop = 470-ohm and Rbottom = 56-ohm with VCC = 3.3V to set the bias to 350mV .

    Kind regards,
    Lane