Other Parts Discussed in Thread: CDCE6214-Q1, LMK03318, LMK03328, USB2ANY, LMK61E2,
Hi,
after a long fight and experiments we have not succeeded in making LMK61Exx work in the fractional tuning mode. We would like to use it in the fractional mode as a ultra-low jitter, high-frequency audio clock but it does not work as we expect reading datasheet.
Moreover, we checked with two different pieces LMK61E07-SIAT and LMK61E2BBA (125 MHz part) and not only do they not work as in DS but also each behaves differently (!).
The E2 starts in the INTEGER mode and after setting it to the fractional mode its frequency can be fractionally adjusted up to NUM\DEN = 0.5 (but not at least 1.0 as we would expect). A change of NDIV from 50 to 51 results in frequency of 126.3MHz instead of 127.5MHz, i.e. approx. half the expexted step. When NUM/DEN gets more than 0.5 the tuning stops.
The E7 part when powered up at default 70,67 MHz can be fractionally tuned higher (so starts in the fractional mode) up to NUM\DEN = 1.0. However, if the INT is changed more than 2% then output frequency stops reacting to tuning at all.
Generally, based on the datasheet we would expect tuning to +/-10%, since VCO starts at approximetly 5.0GHz and have the tuning range 5.1 +/- 0.5GHz (with equals +/-10%).
We would like to ask first how the INT + NUM\DEN tuning works in general. We would expect that INT should allow to tune within the VCO range = 4.6...5.6 GHz, even if that would generate glitches.
Second question is about NUM\DEN, could it take values greater than 1.0?
And the third question can you please provide hints what we should change in the registers so that it would allow full use of fractional mode at all frequencies ?
For convenience we scanned all the register values for the E07 part (as set at default) which allows to tune from it's default values up and down, but it does not work when the INT is changed by more than 1-2% (e.g. if the original R26 value (49) is changed to 52, it works only if we change values to 48, 50 or 51).
R0: 16
R1: 11
R2: 51
R3: 3
R4: 137
R5: 133
R6: 140
R7: 0
R8: 178
R9: 0
R10: 1
R11: 0
R12: 66
R13: 163
R14: 32
R15: 5
R16: 2
R17: 127
R18: 0
R19: 25
R20: 0
R21: 2
R22: 0
R23: 70
The source of clocking is a quite critical part of our high-end class D amplifier product therefore we have asked detailed questions and would like to be aware how to achieve best possible phase noise performance.
And we would like to make sure if it is actually the best part in TI offer to meet our highest requirements for high-frequency (approx. 400MHz) master audio clock that we intend to synchronize (using custom control logic) to the incoming audio clock. We would also very much welcome suggestions if there is a better part to use for this purpose.
Regards, Pawel
