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CDCE6214-Q1: Related to output jitter and unused output floating

Part Number: CDCE6214-Q1

Hello,

Im use CDCE6214-Q1 recommended by you for jitter cleaner....

1: what is output jitter at 2MHz and 74.25MHz

2: In datasheet no details for un-used output pin because unused output create floating so, what we can do for this...

please check attached schematic in PDF and provide solution...

drawing.pdf

  • Hi Phew,

    1. Max jitter is stated in the datasheet:

    2. Unused outputs should be disabled in the software and left floating.

    I'm a bit confused with the schematic. Do you plan to use XTAL, SE/Diff SECREF or PRIREF? We don't recommend tying all VDD pins together.Also, each VDD pin should have at least one capacitor placed close to pin in order to suppress noise.

    Regards,

    Hao

  • 1: I'm use only one input pin at a one time...

    2: I'm use 74.25mhz oscillator (X1G004451009612) for input frequency....

    3: all vdd supply are same(3.3V)...so we connected together.....

    4: should i need to separate ferrite bead and capacitor to all vdd pin

  • I see. I still recommend using ferrite bead to separate VDD pins, because VDD_REF can be very noisy (VDD for digital reference level), and VDD_VCO is very sensitive to noise. You don't want noise from reference and output to be coupled into VCO. Connecting VDDO_12 (VDD for output 1 and 2) and VDDO_34 can result in crosstalk between outputs if they have different frequencies, which is true in your case.

    Regards,

    Hao

  • I use only one output ( pin22 or pin10 for 2MHz ) at a one time....and also one input ( pin5 or pin1 for 74.25MHz )...

    so, it  create coupling and crosstalk between input and output pin...???

  • OK then VDDO_12 and VDDO_34 can be tied together. 

    Regards,

    Hao

  • nice talk with you,

    Thank you for your response....

    can i get your email id to direct communication...because if, i face any problem related to circuit debug then i can call you through mail...

  • Hi Phew,

    Please contact a local FAE (Field Apps Engineer) for more help with design and debug. He/She can work with you closely and locally.

    Regards,

    Hao

  • okkk, Thank you....

  • Hello,

    No vss(GND) pin in this IC....

    pin 25(DAP) connected to GND but it's use like thermal PAD for IC...

  • Hi Phew,

    The DAP is used as ground reference.

    Regards,

    Hao

  • Hello Sir,

    please find attached layout image and check it, 74.25MHZ trace is too long it will create jitter and noise or not 

    i know 74.25MHz trace is long but no more option to route it...

    cdce6214.pdf

  • I see. I still recommend using ferrite bead to separate VDD pins, because VDD_REF can be very noisy (VDD for digital reference level), and VDD_VCO is very sensitive to noise. You don't want noise from reference and output to be coupled into VCO. Connecting VDDO_12 (VDD for output 1 and 2) and VDDO_34 can result in crosstalk between outputs if they have different frequencies, which is true in your case.

  • did you find a solution for this problem 

    2: In datasheet no details for un-used output pin because unused output create floating so, what we can do for this... !!

    https://tutuapp.uno/ , https://9apps.ooo/ , https://showbox.kim/

  • I use ferrite bead to separate VDD pins. see attached pdf...

    my question is im use out0 bypass output 74.25MHz frequency, is trace very large in layout so it create noise (or jitter) in output or not ...

    1667.drawing.pdf

    and 

    2: In datasheet no details for un-used output pin because unused output create floating so, what we can do for this... !!

    solution provided by you ( Unused outputs should be disabled in the software and left floating.)..

     

  • Hi Phew,

    Y0 and Y1 are on the opposite sides so the crosstalk between the two will be minimal. However, you can always reduce the thickness of first layer in order to reduce the width of 74.25MHz trace, if that's what you mean by trace being very large.

    For unused outputs, disable them in software and leave them open in schematic.

    Regards,

    Hao