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LMK04828: LMK04828 & LMX2594 phase delay step size

Part Number: LMK04828
Other Parts Discussed in Thread: LMX2594, TIDA-010132

Hello team,

my customer is refer to TIDA-010132 reference design for multi-AFE synchronization, however is our reference design schematic have both LMK04828 and LMX2594 can adjust phase delay. customer is asking other than better phase noise what is the benefit of LMX2594? what are phase delay step size compare LMK04828 and LMX2594?

Thanks & Regards

Eddie

  • Hi Eddie,

    The LMK04828 is comprised of integer PLLs and acts as a clock generator / jitter cleaner for frequencies below 3.1 GHz, with 7 DCLK and 7 SYSREF outputs. It supports both analog and digital delay adjustments. Digital delay allows adjustment of up to 32 clock cycles on DCLK channels, and up to 8191 global + 11 local clock cycles on SYSREF channels, in one-half VCO / clock-distribution path clock cycle increments. So for example with a VCO frequency on PLL2 of 3000 MHz, digital delay would allow adjustment of 1 / 3000 Mhz = 150 ps step size. Analog delay allows adjustment of between 500 ps to 1075 ps in 25 ps increments, or can be disabled for 0 ps adjust. Note that analog delay adds some phase noise, and the exact analog delay value experiences some drift across PVT (compared to digital, which varies significantly less).

    The LMX2594 is a fractional RF PLL with two outputs, which normally can produce an output frequency between 10 MHz and 15 GHz. Only one of these outputs can be used as a SYSREF, and the SYSREF output frequency is limited to between about 200kHz and 187.5 MHz. The SYSREF output phase can be adjusted from 0 ps to 2223 ps with 9 ps step size. Additionally, the phase of the high-frequency device clock can be further tuned by adjusting the MASH seed value - the exact adjustment calculation is involved, please see section 7.3.11 in the LMX2594 datasheet for more information. The major takeaway, however, is that the phase shift is inversely proportional to the N-divider fractional denominator (even when operating in integer mode), so the phase adjustment can conceivably be reduced to almost arbitrarily small amounts on a single-cycle basis.

    The reason for the layered LMK04828 / LMX2594 design in TIDA-010132 is primarily to take advantage of the excellent phase noise performance of the LMX2594 for the DCLKs, while also utilizing the low skew and adjustable phase delay options on the more flexible, multi-output LMK04828 to generate the OSCin and SYNC inputs to the LMX2594s. Either device can generate the SYSREF signal, and the choice of which one to use comes down to which critical timing the designer wishes to manage; SYSREF from LMX2594 requires carefully timing the LMX2594 SYSREF_REQ signal, while SYSREF from LMK04828 requires careful adjustment of the DCLK phase of the LMX2594 to meet setup and hold requirements (since LMK04828 delay adjustment is usually too large step size). Additionally, the LMK04828 can be configured with a deterministic phase relationships across multiple devices, which can be useful in building phase-aligned clock trees distributed to many (>7) devices. Of course, the cost of an LMX2594 will be much greater than the cost of an LMK04828, so it makes the most sense to use the LMX2594 in situations where high frequency or exceptional performance justify the cost.

    Regards,