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LMK61E07: Loss of clock during recalibration

Part Number: LMK61E07
Other Parts Discussed in Thread: CDCE6214-Q1, LMK03318, LMK05318

Hi,
as mentioned in the related thread we are trying hard to make LMK61 our main ultra low-jitter audio clock. One of our key requirements is that the output frequency needs to be adjusted to the incoming audio, in particular switch between 44,1k and 48k audio clock domains which requires an unavoidable change in PLL_NDIV. That, as we learnt in the related thread, requires a VCO recalibration command (toggling one of R72 bits). Unfortunately the VCO recalibration has a side effect that for the period of recalibration the LMK stops generating the output clock which is a big problem in our design.

Is there any way around this problem ?

If not maybe TI has in the offering IC-s with the same/similar VCO engine that offer uninterrupted clock output function ?

Regards, Pawel

  • Pawel,

    This device supports glitchless frequency margining (search for "DCXO" in the datasheet). It should be able to solve your problem.

    Regards,

    Hao

  • Hi Hao,
    can you please check against practice the answers that are provided, our question was based on practical observation and I think was clearly stated, it is specifically about the output clock that does disappear after the VCO calibration command is sent (i.e. toggling R72[1] bit) for approximately 10ms. 
    On the other hand in the previous (locked) related thread TI recommended that after each tuning command this VCO calibration command should be issued. Then we'd have constant 10ms periods of missing clock. This cannot be called glitchless operation.
    We are very confused for the moment and hope for clarification.

    Regards, Pawel

  • Hello Pawel,

    OK I'll check it on the bench. Meanwhile, did you use the DCXO mode that was mentioned in the previous post? You don't need to toggle the recal bit for frequency margining.

    Regards,

    Hao

  • Hao,
    yes, we used frequency margining from the very beginning. We researched that in practice very carefully since similarly as you suggested we thought it would precisely solve our problem. But it soon became visible in our experiments that frequency margining has quite tight limitations that are not documented in the datasheet. What we observed was that without to toggling VCO calibration reset we were able to marginally tune within less than a single INT unit value, which is for some audio sample rates insufficient for us.
    That is why we asked very analytical and targeted questions in the previous.locked thread, to get information missing from the datasheet right from the TI source .
    We could not understand each other as to these questions because you suggested toggling VCO calibration. Yes, it moves the frequency margining span to a new center frequency but has a critical drawback that it switches off the output clock. We are also unsure if frequency margining without toggling VCO calibration actually keeps the datasheet parameters or they e.g. graduallly decline. So at least it seemed in our tests that more than 0.3 INT unit from the center frequency new spurs appeared. 

    So summing up we strongly need extended and deepened information how the frequency margining works, what are the limitations and jitter parameters behaviour.
    Alternatively, if you confirm our observations concerning this chip limitations please advise if there is any similar TI chip that e.g. mainatins the clock while VCO calibration.

    Regards, Pawel

     

  • Hi Pawel,

    Sorry for the delay. I'll probably be able to do this test on the week of Dec 2nd.

    Regards,
    Hao

  • Hi Pawel,

    I agree that the tuning range in DCXO mode is less than one integer N divider value. What tuning range do you need? Typically glitchless frequency margining doesn't provide very wide tuning range because PLL has to recalibrate at a certain point. 

    There are two ways of frequency margining. One is to adjust numerator of N divider like LMK61E07, the other is to adjust the load capacitance of crystal. The first approach naturally create many spurs because of fractional PLL. The second approach, however, generates clean output because it works in integer mode all the time. LMK61E07 potentially also supports the second way of frequency margining through register  "XO_CAPCTRL".

    Devices that support frequency margining are: CDCE6214-Q1, LMK03318, LMK05318 and many others. CDCE6214-Q1 may work for you but others may be too complicated for your application. 

    Regards,
    Hao

  • Hi Hao,

    thanks for the check-up. So our problems/missing LMK61 functionalities have been confirmed but unfortunately your response does not help us to progress with our project yet.
    Can you please advise us if there is an IC in Texas offering that has such features:

    - has phase noise at the level of LMK61 or better,

    - has wider tuning range than LMK61 or can maintain somehow the clock during calibration ?

    I do not if the CDCE6214-Q1 maintains the clock during calibration ? But it seems inadequate for our application since it has a medium grade jitter performance while we need upper shelf available.

    Regards, Pawel

  • Hi Pawel,

    What output frequency and tuning range do you need? From what I understand, you need glitchless output while output frequency changes, is that right? As for devices that support frequency margining, CDCE6214-Q1, LMK03318 and LMK05318 are featured devices with different jitter performance levels. LMK05318 has the best jitter performance (~50fs), then LMK03318 (100~120fs), then CDCE6214-Q1 (~400fs).

    Have you tried tuning the load capacitance of LMK61E07? Does that meet your tuning range? I've seen many applications that need glitchless frequency margining, but none of them require a very wide tuning range. Most of them only need within +/-1000ppm.

    Regards,
    Hao