Other Parts Discussed in Thread: CDCE6214-Q1, LMK03318, LMK05318
Hi,
as mentioned in the related thread we are trying hard to make LMK61 our main ultra low-jitter audio clock. One of our key requirements is that the output frequency needs to be adjusted to the incoming audio, in particular switch between 44,1k and 48k audio clock domains which requires an unavoidable change in PLL_NDIV. That, as we learnt in the related thread, requires a VCO recalibration command (toggling one of R72 bits). Unfortunately the VCO recalibration has a side effect that for the period of recalibration the LMK stops generating the output clock which is a big problem in our design.
Is there any way around this problem ?
If not maybe TI has in the offering IC-s with the same/similar VCO engine that offer uninterrupted clock output function ?
Regards, Pawel