LMK04832: Why PLL2 locked when setting internal VCO1 to 3440.64MHz (under PLL1 power down)

Hsinru Chiang

Prodigy 70 points

Part Number: LMK04832

Hi,

I tried several settings with PLL1 but PLL1 never locked.

So, I now power down PLL1, use only PLL2. I tested 2949.12MHz, 3194.88MHz and 3440.64MHz for VCO1.

And PLL2 locked only when VCO1 is set to 3440.64MHz (N divder = 14).

But from spec, VCO1 should be within 2945 to 3255MHz.

Is there any reason why this happened? And any suggestion to let PLL2 locked under VCO1=2949.12MHz w/wo PLL1?

Thank you.

LMK04832_VCO1_3440MHZ.tcs

over 4 years ago

0 Liam Keese over 4 years ago

TI__Genius 12705 points

Hello,

the VCO's are able to lock across the specified range provided the other parameters are within spec.

Can you provide more details on your test conditions?

Are you using TI EVM or your own PCB design?

Thank you,

0 Hsinru Chiang over 4 years ago in reply to Liam Keese

Prodigy 70 points

Our circuit is just like the schematic in this link. (https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/48/mach_5F00_LMK04832.png)

We put a 122.88MHz VCXO on OSCin for PLL2. No input on CLKin0, 1, 2. OSCout buffer is powered down.

We probe output signals onto oscilloscope (500MHz, 4.5GSPS MAX) to see whether we get accurate clocks.

R and N (and prescalar) dividers are only parameter to make PLL2 lock in this case.

In our test, when R =1, N=14, and prescalar =2, it locked. (An indicator LED lights on)

But if OSCin = 122.88MHz, with these parameter value, VCO1 would be 3440.64MHz (From TICO pro), which is out of range stated on the spec (2945 to 3255MHz).

How could I fix to make sure VCO1 is within the range?

0 Dean Banerjee over 4 years ago in reply to Hsinru Chiang

TI__Mastermind 27581 points

Hsinru,

The VCO frequency would need to be a multiple of 122.88 MHz.

I calculate the following possibilities for the VCO frequency:

2457.6 MHz

2949.12 MHz

3072 MHz

3194.88 MHz

Regards,

Dean

Clock & timing

Clock & timing forum

LMK04832: Why PLL2 locked when setting internal VCO1 to 3440.64MHz (under PLL1 power down)