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LMK04828: What is the READ timing on LMK04828 SCK and SDIO? What is the name of the standard this 3-wire half-duplex "SPI" bus is compliant to?

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Part Number: LMK04828

HI,

I need some clarifications of the LMK04828 3-wire SPI interface.  I have been trying to look for the standard for this 3-wire SPI.  There are many SPI documents in the internet, but most of them are for the 4-wire SPI (SCK, CS, MISO, MOSI).  There are some for 3-wire SPI (SCK, MISO, and MOSI) , but they are not the same SPI used in the LMK04828.    My questions are:

1. What 3-wire SPI standard this LMK04828 is based on?

2.  For a READ on the SPI, is there a requirement for the master to do something on the SCK (such as stretching or delaying the SCK ) at the last bit of address transfer, so there is enough time for the LMK04828 SDIO pin turns around from input to outputting the 8-bit data?   And what is SCK delay or turn around timing requirement?

Thanks,

Meng     

  • Hello,

    The 3 wire SPI implementation is a half duplex variant of 4 -wire SPI.  I believe it is migration from previous microwire interface.

    There are no requirements for clock stretching. Timing is provided in table 7.6 

    Kind Regards,

    Liam

    Liam Keese

    Clock and Timing Systems & Applications


    To design your own Clock Tree solution, visit WEBENCH Clock Architect ​​​​

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  • In reply to Liam Keese:

    thanks Liam.

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