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Part Number: LMK04832
Hi, I'd like to use the LMK04832 (EVM) in external VCO/clock distribution mode but am not sure what I need to program on the CLKinX Control, PLL 1 and 2, and Clock Output pages on TICS Pro. Please see below more details on my application. I am feeding a high frequency input clock to CLKin1 - a 1.25 to 3 GHz sine wave. I will need two device clock outputs from the LMK device - divided down by either 4 or 8, and a SYSREF pulsed signal. It doesn't look like the PLL/VCO is locked as the divided down outputs are not at the correct frequencies. I am also not seeing any SYSREF output - do I need to use the CLKIN0 input for this to work? But I can only provide a high frequency input signal, which will be beyond the normal CLKIN* frequency range.
I have tried a few more things. If I bypass/power down PLL1 and use PLL2, then apply the output from either the internal VCO1 or VCO2 to the Clock distribution network, I see intermittent lock on PLL2 (the onboard LED is flashing), and CLKout/output frequencies are close but not quite correct. So I change the input frequency, the output frequency doesn't actually follow.
Can someone please help? I have tried using the "CLKin1 drives Clock Distribution" mode in the GUI/TICS Pro and programming other settings based on my understanding of the Functional Block Diagram in the datasheet but I am stuck at this point. Thanks!
LMK04832 in distribution mode does not use the internal PLLs, it just sends an external VCO signal from CLKin1 to the SYSREF/CLKout dividers. There is also PLL2 + External VCO configuration, where the internal PLL2 is used and an external VCO is used for feedback. In distribution mode, the PLLs can be disabled (there is no way to lock if the PLL is not used). In PLL2 + external VCO configuration, PLL2 must be enabled at a minimum. I will assume you want distribution mode. See below, note that VCO_MUX is set to CLKin1 for receiving external VCO for distribution (CLKin1 is specially able to take high frequency input > 750 MHz).
To set up the SYSREF path, the following conditions must be met:
From there, the quickest way to check if SYSREF is functioning is to use the SYSREF_MUX to set continuous SYSREF mode. The internal SYSREF generator will begin dividing the clock distribution path signal to generate the SYSREF output.
Outputs should also be configured as desired. Note that SCLKx_y_PD must be set to 0 to enable the SYSREF path on channels x or y, DCLKx_y_PD should be set to 0 to enable the device clock output on channels x or y, and CLKoutx_y_PD should be set to 0 to enable output from CLKoutx or CLKouty. CLKoutX_SRC_MUX and CLKoutY_SRC_MUX can be used to choose device clock divider source or SYSREF divider source for CLKoutX or CLKoutY. As an example, here is a setup which uses 3 GHz VCO input, divides by 8 on CLKout0, and uses SYSREF divide of 300 on CLKout1.
Once you have confirmed the operation of the CLKout channels and the dividers/SYSREF circuit, you can set the SYSREF in pulser mode by setting the SYSREF_MUX:
The SYSREF pulser must also be enabled by setting SYSREF_PLSR_PD = 0. The SYSREF pulser can be triggered by a SPI source (writing to the pulse count register) or by sending a signal on the SYNC pin. This control is selected by the SYNC_MODE register:
Let us know if you need further assistance, we understand that the clocking parts are complex and can have a steep learning curve!
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In reply to Derek Payne:
Thank you very much for the detailed response.
I have tried distribution mode before and couldn't get it to work somehow. I just tried again with the settings you provided but the output frequencies are completely off, and the signal looks very unstable - same behavior as before. I will double check this with a different EVM tomorrow.
I'd like to use the PLL2 + External VCO configuration. Can you describe/show me how to set up the PLL 1 and 2 page for this mode?
I noticed that PLL2 wouldn't try to relock after I change its settings (divider, mux selections, etc.) in the GUI. How do I manually trigger a "relock"/re-acquisition? I remember seeing PLL reset buttons on other clock chip GUIs, such as the LMK04610, but could not find this in the LMK04832 GUI.
In reply to Joyce Ng1:
I am not very familiar with this product, but is this issue still unresolved?
In reply to Dean Banerjee:
Thanks for the follow-up. Yes, I still have a number of questions.
And how do I trigger a "relock" on PLL2? I have tried the SYNC pin after enabling PLL2R_SYNC_EN (on the CLKinX control page).
I have not been able to get PLL2 to lock, other than using the default setup/config. What are the valid ranges for OSCin (with External VCXO selected as the OSCin Source) and the PLL2 PD Freq? According to the LMK04832 datasheet, the R2, N2, and N Cal dividers can be set to almost any value. I am trying to use PLL2 with a high frequency input clock to CLKin1 - a 1.25 to 3 GHz sine wave.
I noticed that the Import/Export hex register value functions on the GUI/TICS Pro don't seem to work correctly. If I export all the reg values for a given setup, and then import them after restarting the GUI and resetting the LMK device, not all the settings are preserved. Saving and loading .tcs files seem to be fine but we need a way to load register values back using Python.
1, An example for PLL2 only with external VCO
2, Note in Datasheet:
When using the internal VCO, PLL2_N registers 0x166, 0x167, and 0x168 must beprogrammed after other PLL2 dividers are programed to ensure proper VCO frequencycalibration. This is also true for PLL2_N_CAL registers 0x163, 0x164, 0x165 whenPLL2_NCLK_MUX = 1. So if any divider such as PLL2_R is altered to change the VCOfrequency, the VCO calibration must be run again by programming PLL2_N.Power up PLL2 by setting PLL2_PRE_PD = 0 and PLL2_PD = 0 in register 0x173 beforeprogramming PLL2_N.
3, Always save .tcs as your design document. The .tcs includes all frequency information, which can export hex register file for your programming.
Hex register file includes divider information, but no frequency information, which can't be imported by TICS Pro to show all GUI display.
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