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Part Number: CDCE913
I'm facing an issue of I2C byte access.
Upper figure shows byte-write access to 0x2. I can see ack. Then bottom figure shows access to 0x1, and nack is issued. Is my operation wrong?
Are you able to detect the slave address shown in datasheet table 7? Also check out datasheet section 8.5. There are many reasons why I2C doesn't work. First make sure that you are able to scan and set the correct slave address, then choose a R/W register and do a byte write and byte read see if you can read back what you write. Avoid read only registers for this kind of sanity check.
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In reply to Hao Z:
Thank you for your comment. What I confirmed are below.
1-1) sent b'1100101 as slave address
1-2) sent b'0 to write register.
1-3) confirmed ack from CDCE913
1-4) send b'10000001 to write to address 0x1
1-5) confirmed nack from CDCE913
2-1) sent b'1100101 as slave address (same as 1)
2-2) sent b'0 to write register (same as 1)
2-3) confirmed ack from CDCE913 (same as 1)
2-4) send b'10000010 to write to address 0x2
2-5) confirmed ack from CDC
In reply to user6229582:
Not sure I understand why MSB = 1 for (1-4) and (2-4). There's no need for start condition after 7 bits of slave address + 1 R/W bit, if that's what it means. Instead you should probably write 00000001b for address of R0x1, get an ack, then write 8 bit data.That's one byte write cycle.
Because I would like to try byte R/W operation, I added '1' to bit-7 of command code. Actually I tried both '0' and '1' as MSB of command code, but I got same result.
I see. The sequence itself looks correct to me then. Are you able to communicate to other slave devices on the same bus?
No. It is only one device which is connected to these bus.
OK. But have you used the same controller / platform to successfully program other I2C devices previously? This is because I'm not sure if the ack you got was valid because i can't tell whether it's pulled down by the slave or actually by the master (just by extending the LSB, because you always get an ack when the last bit is 0, and a nack when the last bit is 1). Is there a functionality in your platform that can scan I2C bus? The best sanity check that I can think of is to scan the I2C bus instead of directly setting the slave address. If you can find the address by scanning then it means that the I2C really is working.
Actually I designed this I2C master for this device so it isn't proven. But in my simulation, I2C master is waiting ack/nack after register address.
Unfortunately there is no scan function...
I see. Can you separate the two for debugging? Otherwise there's more than one variable and it's hard to know which one is not working. Can you use a slave device that you're familiar with and validate the master first before trying to make the two work together?
I found the root cause. my design isn't met hold time. Now it seems that the device is working correctly.
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