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Part Number: LMK04208
One of my customer is using LMK04208 for ZCU111 Xilinx RFSoC. The output Clock frequencies required is as below.
CLKIN0 -> 122.88 MHz
CLKIN1 -> terminated in connector
Customer requirement is: Feed 10MHz to CLKIN1. Do not use CLKIN0.
Customer have arrived on the values for the configuration they require. Can you please review/validate the attached configuration?
Regards, Shinu Mathew.
In reply to Shinu.V.Mathew:
Here is an example.
1, Calculate GCD for 10 MHz, 12.8 MHz and 7.68 MHz --- > 40 kHz
2, Set PDF1 = 40 kHz
3, Select Feedback_MUX from CLKout0 7.68 MHz
4, Increase CP1 to 1.6 mA to against VCXO leakage current under low frequency PDF condition
5, Set PLL1_WND_SIZE to 40 ns in "User Controls" sheet to against VCXO leakage current
If there is no necessary to use 0-delay, then we can use 200 kHz PDF1 for 10 MHz and 12.8 MHz references, which can defense VCXO leakage current better than lower 80kHz or 40 kHz.
For the topic about VCXO current leakage, refer to my notes, attached.
4370.VCXO Leakage Current and PLL Lock v1.0.pdf
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More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
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