Other Parts Discussed in Thread: ADS42JB46EVM, LMK04821, ADS52J65EVM, LMK04832EVM, LMK04832
Hi
We would like to use LMK04828 in distribution mode (both PLL off) where source clock has phase noise <-154dBc/Hz@1kHz.
Is the device able to distribute such clock without a significant phase noise degradation at this offset (atleast to -148dBc/Hz)?
Thanks,
Daniel