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LMK03318: unstable clock generation issue

Part Number: LMK03318

To the person concerned
Now I face a strange problem with LMK03318.
The problem is that the clock output on LMK03318 does not occasionally occur when the system boots.
This issue does not occur on all LMK03318 each time.
- . When the system boots up, the output sometimes generates and does not, even if the sample is the same.
- Some boards manufactured on the development board at the same time have and do not have a clock output for each board at the same

For boards that do not produce output, the following modifications result in the clock output:
- With the attached file in the set value state, change the register below as follows:
Keep R59 at 0x42 and change R56 (PLL_POST_Divide) to 0x0a, R33 (OUTPUT_DIV), R36, R38, R40, R42, R44 to 0x0a => 156.25MHz

Could you please review the settings in the attached file for problems?

Appreciate your help in advance

HexRegisterValues-20191015_2_Clkoutput_OK.txt
R0	0x0010
R1	0x010B
R2	0x0233
R3	0x0302
R4	0x0401
R5	0x0500
R6	0x0600
R7	0x0700
R8	0x0802
R9	0x0900
R10	0x0AA0
R11	0x0B00
R12	0x0CDD
R13	0x0D00
R14	0x0E3D
R15	0x0F20
R16	0x1000
R17	0x1103
R18	0x1200
R19	0x1300
R20	0x14FF
R21	0x15FF
R22	0x16FF
R23	0x1703
R24	0x1800
R25	0x19A0
R26	0x1A00
R27	0x1B88
R28	0x1C28
R29	0x1D0F
R30	0x1E40
R31	0x1F28
R32	0x2028
R33	0x210F
R34	0x2228
R35	0x2328
R36	0x240F
R37	0x2514
R38	0x260F
R39	0x2714
R40	0x280F
R41	0x2914
R42	0x2A0F
R43	0x2B14
R44	0x2C0F
R45	0x2D08
R46	0x2E01
R47	0x2F00
R49	0x3108
R50	0x3253
R51	0x3303
R52	0x3400
R53	0x3501
R54	0x3600
R55	0x3700
R56	0x3806
R57	0x3908
R58	0x3A00
R59	0x3B40
R60	0x3C00
R61	0x3D00
R62	0x3E00
R63	0x3F00
R64	0x4000
R65	0x4101
R66	0x420C
R67	0x4304
R68	0x4401
R69	0x4504
R70	0x4607
R71	0x4701
R72	0x4800
R73	0x4900
R74	0x4A00
R75	0x4B00
R76	0x4C00
R77	0x4D00
R78	0x4E00
R79	0x4F00
R80	0x5000
R81	0x5100
R82	0x5200
R83	0x5300
R84	0x5400
R85	0x5500
R86	0x5600
R87	0x5700
R88	0x5800
R89	0x59E3
R90	0x5A01
R91	0x5B32
R92	0x5C01
R93	0x5D59
R94	0x5E01
R95	0x5F86
R96	0x6001
R97	0x61BE
R98	0x6201
R99	0x63FE
R100	0x6402
R101	0x6547
R102	0x6602
R103	0x679E
R104	0x6800
R105	0x6900
R106	0x6A05
R107	0x6B0F
R108	0x6C0F
R109	0x6D0F
R110	0x6E0F
R115	0x7308
R116	0x7419
R117	0x7500
R118	0x7607
R119	0x770D
R120	0x7801
R121	0x790F
R122	0x7A0F
R123	0x7B0F
R124	0x7C0F
R129	0x8108
R130	0x8219
R131	0x8300
R132	0x8403
R133	0x8501
R134	0x8600
R135	0x87D7
R136	0x8802
R137	0x8910
R138	0x8A00
R139	0x8B01
R140	0x8C58
R141	0x8DE8
R142	0x8E7E
R143	0x8F07
R144	0x9000
R145	0x9100
R169	0xA940
R172	0xAC24
R173	0xAD00

Thank You

Mark Kim

  • Hello,

    Thank you for attaching the register files this helps to understand the settings.  If you have some additional information on the power up timing this would also be helpful.

    Regards,

  • Dear Liam

    appreciate your prompt reply.

    In case of power up, Customer has applied Single Supply rail according to Figure 83 Recommendation for Power Up from single supply Rail.

    If you need measuremnet data with scope, Please let me know which pins are meansured together with power rails.

    the attached figure is current  configuratin, Just in case, please look into it

    Yesterday,  I missed input and output clock frequency information.

    Input Clock for PRI and SCE is 156.25MHz

    Output clock for all Output is 156.25MHz

  • Hi Liam

    Could you give me your idea for this ticket?

    thank you

    Best Regards

    Mark Kim

  • Hi Mark,

    In order to gain some more insight to the issue, could you please try pulling the PDN low for around 2 ms and seeing if this corrects the output?

    It would also be beneficial to see a plot of VDD and PDN versus time to make sure the ramp is monotonic and that PDN doesn't ramp up too quickly. Do you think it would be possible to provide this?

    Also I can't seem to locate the PDN pin in the schematic you sent. Could you let me know if the pin is floating or has a capacitor on it?

    Best,

    Adam Siismets

  • HI Adam

    In case of PDN, It is connected to CPLD and external PU resistor. I reckon you consider to take additional care to prevent unsuccessful PLL calibration.

    For this case, Datasheet recommends two ways : Add R-C time constant with 200Kohm resistor and Provide a larger PLL Closed loop delay by R119 register.

    -. they are used to add dealy for PLL Loop to stablize. So before your mail, We added dozens of milliseconds to PDN pin.

    - . With added dealy on PDN pin, The phenomenon of the problem seems to occur less. But it's not a complete solution.

    Let me list up problems we faced again until today.

    1. when power up, We expected default clock output before register setting. --> Frequently, some of ICs didn't generate clock output.

      At this time, when invoked software reset, the clock outputs were observed.

     this is first problematic phenomenon.

    Q1) which one can be affected for default operation?

    2. Second problem is related to N-Divider 's value in PLL Block.

    With Wizard tab on TICS pro, We got 5 recommended combinations as below figure and applied them in sequence to find out which one is better.

    As figures, N-Divider column recommended decimal 64 or 66. When applied one of combinations which N-divider was 64, the clock output was not observed.

    In order to get clock output, 66 was right value for N-Divider 

    Q) why did only 66 work?

    thank you

    Best Regards

    Mark Kim

  • Hi Mark,

    The register settings you sent in your initial message don't seem to match what you have in that last post. The configuration you sent has all outputs set to 50MHz as well as a VCO frequency out of the recommended operating range. Do you think you could send the latest register settings so that we may better assist you?


    Regards,

    Adam Siismets

  • Hi Adam

    When I saw first post, I found out I missed PRIREF and SECREF frequency. Due to it, you can have differnet output clock.

    They are 156.25MHz. With register values which I attached file plus input clock frequency, VCO and PFD frequency were set in the recommended range.

    And, in case of test result in lost post, While debugging problem, Customer tried many things. Some of them were to adopt register setting recommended on Wizard tab.

    - with last test, Customer found out that when PLL_NDIV(R58,59) had Decimal 64, the Clock outptu was not generated normally even register values was recommended on TICS.

    - As figure in previous post, one of Calcuated setting on Wizard had PLL_NDIV=66 and when it was adopted, Clock output was generated.

    Current Problem and question are  same with question and problem in previous post.

    - From time to time, When powered up, Default clock was not generated.

    - When applied 64 to PLL_NDIV, Clock output was not occurred.

    5756.HexRegisterValues-20191015_2_Clkoutput_OK.txt
    R0	0x0010
    R1	0x010B
    R2	0x0233
    R3	0x0302
    R4	0x0401
    R5	0x0500
    R6	0x0600
    R7	0x0700
    R8	0x0802
    R9	0x0900
    R10	0x0AA0
    R11	0x0B00
    R12	0x0CDD
    R13	0x0D00
    R14	0x0E3D
    R15	0x0F20
    R16	0x1000
    R17	0x1103
    R18	0x1200
    R19	0x1300
    R20	0x14FF
    R21	0x15FF
    R22	0x16FF
    R23	0x1703
    R24	0x1800
    R25	0x19A0
    R26	0x1A00
    R27	0x1B88
    R28	0x1C28
    R29	0x1D0F
    R30	0x1E40
    R31	0x1F28
    R32	0x2028
    R33	0x210F
    R34	0x2228
    R35	0x2328
    R36	0x240F
    R37	0x2514
    R38	0x260F
    R39	0x2714
    R40	0x280F
    R41	0x2914
    R42	0x2A0F
    R43	0x2B14
    R44	0x2C0F
    R45	0x2D08
    R46	0x2E01
    R47	0x2F00
    R49	0x3108
    R50	0x3253
    R51	0x3303
    R52	0x3400
    R53	0x3501
    R54	0x3600
    R55	0x3700
    R56	0x3806
    R57	0x3908
    R58	0x3A00
    R59	0x3B40
    R60	0x3C00
    R61	0x3D00
    R62	0x3E00
    R63	0x3F00
    R64	0x4000
    R65	0x4101
    R66	0x420C
    R67	0x4304
    R68	0x4401
    R69	0x4504
    R70	0x4607
    R71	0x4701
    R72	0x4800
    R73	0x4900
    R74	0x4A00
    R75	0x4B00
    R76	0x4C00
    R77	0x4D00
    R78	0x4E00
    R79	0x4F00
    R80	0x5000
    R81	0x5100
    R82	0x5200
    R83	0x5300
    R84	0x5400
    R85	0x5500
    R86	0x5600
    R87	0x5700
    R88	0x5800
    R89	0x59E3
    R90	0x5A01
    R91	0x5B32
    R92	0x5C01
    R93	0x5D59
    R94	0x5E01
    R95	0x5F86
    R96	0x6001
    R97	0x61BE
    R98	0x6201
    R99	0x63FE
    R100	0x6402
    R101	0x6547
    R102	0x6602
    R103	0x679E
    R104	0x6800
    R105	0x6900
    R106	0x6A05
    R107	0x6B0F
    R108	0x6C0F
    R109	0x6D0F
    R110	0x6E0F
    R115	0x7308
    R116	0x7419
    R117	0x7500
    R118	0x7607
    R119	0x770D
    R120	0x7801
    R121	0x790F
    R122	0x7A0F
    R123	0x7B0F
    R124	0x7C0F
    R129	0x8108
    R130	0x8219
    R131	0x8300
    R132	0x8403
    R133	0x8501
    R134	0x8600
    R135	0x87D7
    R136	0x8802
    R137	0x8910
    R138	0x8A00
    R139	0x8B01
    R140	0x8C58
    R141	0x8DE8
    R142	0x8E7E
    R143	0x8F07
    R144	0x9000
    R145	0x9100
    R169	0xA940
    R172	0xAC24
    R173	0xAD00
    

  • Hi Mark,

    Can you confirm that you waited for the device to stabilize in the error state before pulling PDN low for 2ms? Again, it would be helpful to see a plot of VDD and PDN vs time to make sure the ramp is monotonic and that PDN doesn't ramp up too quickly.

    As for the N divider problem, could you route PLL RDIV/2 and PLL NDIV/2 to the Status0 and Status1 pins and send plots for the N divider at 64 and 66? This will help verify that the PLL is working properly. I will do the same measurements so that we can compare.

    Thanks,

    Adam Siismets