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Part Number: LMK05318
I am working on a clock synchronized with a GPS signal. This clock will be the input clock of an ADC.
I am testing the LMK05318 through the evaluation board.
If I apply a voltage divider to the original PPS signal (the amplitude of the signal applied to the EVM is 1.76V), LMK05318 toggles (roughly every two seconds) between the holdover state and the PRIREF state. Even when the PRIREF is valid, both the LOPL_DPLL and the LOFL_DPLL flags are checked (the DPLL doesn't lock to the 1pps signal).
Instead, if I apply to the EVM the original 3.3V 1PPS signal, LMK05318 stays in the PRIREF state until the GPS signal is present and then with a delay (in some cases the delay is 40 seconds) returns in the holdover state. However, also in this condition, once the module has recognized the PRIREF signal as valid, the DPLL doesn't lock to the 1 pps signal (both the LOPL_DPLL and the LOFL_DPLL flags remain checked).
As output frequency I have set 4Hz in order to view better the relationship between the 1pps input signal and the LMK05318 output frequency. However, in the real application the output frequency will be 33kHz.
I attach the two configuration files one for the 4Hz output frequency and the other for the 33kHz output frequency. The behaviour observed is the same for both the frequencies generated
In the evaluation board I am using the standard 48.0048MHz XO.
I have applied to the PRIREF input the 1pps signal coming from the module NEO-M8T.
The other inputs (PRIREF_N , SECREF_P and SECREF_N ) are pulled down through a 1k resistor.
The amplitude of the PPS signal coming from the GPS module is 3.3V.
Is it correct in this case to choose "CMOS" as PRIREF interface type?
At the moment I am using only the amplitude validation option.
However, based on another post present in this forum, I am not clear if I should use the 1PPS Phase Detector validation option.
What else I am missing? Thanks in advance
Just letting you know that I'm working on a software update for 1pps configuration. There're a few things to note for 1pps. Let me summarize the procedures (it'll become easier after the software update) and get back to you tomorrow.
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In reply to Hao Z:
Please find attached. LMK05318 1pps 2-7-2020.zip
Sorry for the delay in the reply.
I have made some tests using the configuration file you provide, I have followed the instructions present in the .word file you attached.
I have modified the XO frequency to 48.0048MHz as I am using the XO present on the EVM and I have changed the PRI_REF interface to CMOS.
I have manually set registers R286,R287,R288 and R289 as described in the .word document.
However, in this configuration the Primary Reference is always considered invalid and therefore the DPLL does not lock to the reference. The flag BAW_LOCK becomes one almost immediately after having powered up the board (I have written the configuration in EEPROM).
I have tested the configuration also with different 1PPS signal pulsewidths (10us, 1ms,20ms,200ms and 500ms) as the GPS module (NEO-M8T) we are using is able to configure the output pulsewidth.
I attach a screenshot of the status window. It is the same for all the tests I have made.
What I am missing?
Thanks in advance
1pps default 02-12-2020.tcs
In reply to Gabriele Marocco8:
I'm afraid that the on-board 48.0048MHz XO cannot be used for 1pps configuration. This is because 1pps configuration requires very narrow loop bandwidth (0.01Hz). If the XO has too much wander, then the DPLL will have trouble tracking the phase error. So the 1pps phase detector requires a stable XO because it takes in the jitter of 1pps reference in periods of XO clock. If the XO input has too much wander then the PRIREF_VALSTAT won't be cleared.
A regular TCXO or OCXO with 4.6ppm frequency accuracy should work. For sanity check, you can use an external signal generator which typically has an OCXO inside.
Besides, the input type for 1pps PRIREF or SECREF needs to be SE(50Ohm) instead of CMOS.
Please see attached for XO/reference frequency accuracy requirements.1pps phase detection calculator.xlsx
Thanks for the information.
I have applied a 20MHz oscillator with a frequency accuracy of +/-200ppb (M200F-020.0M) to the XO_P. As suggested in the LMK05318EVM User's Guide, I have removed C80 , soldered C81 (0.1uF) and applied the XO output to the XO_P terminal.
Even with this setup and applying to the PRIREF_P input a 1pps signal with a pulsewidth of 100ms ( the signal is generated by the NEO M8-T GPS module), the 1pps signal is not considered as a valid reference and therefore the locking condition is not reached.
Instead of applying the GPS output signal to the PRIREF_P input I have also tested the configuration with a 1Hz signal 20% duty-cycle coming from a waveform generator. However, also in this condition the PRIREF is not considered valid and the locking condition is not reached..
Do you suggest making some tests with another oscillator?
Sorry for the late response. The oscillator is good enough. Before formal Ticpsro update release, please use this profile:LMK05318.zip
In Ticspro tool bar, go to "select device" -> "import user device" and select the zip file (don't unzip it), then "select device" -> "user devices" -> "lmk05318". Upon loading this profile, go to "default configuration" in the tool bar and load "1pps input" default. You can change XO frequency, click "calculate frequency plan", then click "run script".
Let me know if you still can't get valid PRIREF.
Thanks for the reply. I have uploaded the default configuration "1pps input".
I have made two tests: one applying a 1Hz square wave with 20% duty cycle coming from a function generator and the other applying a 1Hz square wave with a Ton of 10ms coming from the GPS module NEO M8-T.
The XO source is always the 20MHz +/-200ppb of the previous post section.
Unfortunately for both the input configurations, when the "1pps Phase Detector" flag is checked (the threshold is set at 63 3.15udeg) the primary reference is still considered invalid.
Instead, only if I uncheck this flag, the primary reference becomes valid but the DPLL doesn't reach the locking condition.
I understand that the "1pps Phase Detector threshold" takes into account the jitter of the reference input clock with respect to the XO clock, but I don't understand how this parameter is calculated and therefore how to set it (indipendently from the settings present in the default configuration)
Please refer to datasheet 188.8.131.52.6 for illustration. More details are described below:
1. The allowed time interval between current edge and the next valid edge of PRIREF/SECREF should be within (actual XO period) * (REF_VALID_CNT +/- REF_VALID_THR).
2. If the 1pps reference is absolutely accurate, then this time interval error (+/- REF_VALID_THR * XO_period) consists of XO frequency drift, wander and accumulated jitter, where by definition wander does not include frequency drift. If I ignore wander and accumulated jitter and consider only the frequency drift, then after some math, maximum allowed ppm error = REF_VALID_THR / (nominal XO frequency) * 1e6. For example, with 38.88MHz XO and REF_VALID_THR = 63, the maximum allowed ppm error = 1.62ppm.
Can you please attach the .tcs file you used? I'll quickly check a few registers.
Thanks for the explanation. I attach the .tcs file
In order to generate the 1pps signal, I have used a GPS module (NEO M8T) with a timing accuracy of 20ns and a time pulse jitter of 11ns.
I have also test the configuration by applying a 1Hz 20% duty cycle square wave coming from a signal generator with 50ppm accuracy
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