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Original question:

LMK04821: LMK04821

LMK04821: LMK04821_SUPPORT

Lakshmi M B
Prodigy 40 points
Part Number: LMK04821

Hello,

We are using LMK04821 in one of the enodeB design. The reference input of 122.88MHz is applied to CLKIN0.

While tested on RFE board,with LMK input from clkin0/clkin1 We are observing career frequency offset of 4Mhz.

Eg: For center frequency of 800Mhz, career freq of 796.54Mhz is observed(offset of 4).


Could you please help me by changing what register settings on the LMK tool(TICS PRO), we can achieve the career frequency without any offset.

Thanks and regards,

Lakshmi M B

  • 0
    TI__Genius 12705 points

    Hello Lakshmi,

    There should be no offset when the PLL's are locked. Can you please verify lock status?

    Also if you can attach the .tcs file to this string this would be helpful to see for reference.

    Regards,

  • 0 in reply to Liam Keese
    Prodigy 40 points

    Hello Liam Keese,

    Thanks for the reply. I have attached the .tcs file which we are using.

    It is also observed that with OSCin as reference clock input, there was no offset on the career frequency found. 

    Thanks and regards,

    Lakshmi M B

    LMK04821_FINAL.tcs

  • 0 in reply to Lakshmi M B
    TI__Mastermind 29010 points

    Hello Lakshmi,

    This sounds like there is some interference at approximately 4 MHz being coupled into the VCXO power supply/GND or the charge pump supply/GND. First, is the system powered with switching power supplies at around this frequency, or which could have harmonics at this frequency? Second, are there any nearby noise sources operating at this frequency or generating harmonics that correspond to this frequency, that could be coupling into the VCXO?

    Regards,

  • 0 in reply to Derek Payne
    Intellectual 855 points

    Hi Derek,

    Thanks for the reply.

    The offset was observed in two different board designs with same offset problem . The common device is LMK04821. The circuit is taken from AFE76xx board to generate JESD204B clocks. The difference is, we are applying clock input to CLKIN0.

    Now with the attached register settings the carrier offset is gone in both the boards. but we are observing framer status error in the RF card output. Looks like the timing (setup and hold) between DCLKout (Device clock) and SDCLKout (sysref as per JESD204B) is not correct. some delay adjustment to be made. We are trying to debug.

    It would be great if some working configuration for clkin0 is shared.

    Regards,

    Sumathi

    25-2-2020_shawn_clk0.txt 
    R0 (INIT)	0x000090
R0	0x000010
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x00055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010006
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010420
R261	0x010500
R262	0x0106F0
R263	0x010711
R264	0x010806
R265	0x010955
R266	0x010A55
R267	0x010B00
R268	0x010C20
R269	0x010D00
R270	0x010EF0
R271	0x010F11
R272	0x011006
R273	0x011155
R274	0x011255
R275	0x011300
R276	0x011420
R277	0x011500
R278	0x0116F0
R279	0x011711
R280	0x011806
R281	0x011955
R282	0x011A55
R283	0x011B00
R284	0x011C20
R285	0x011D00
R286	0x011EF0
R287	0x011F11
R288	0x012006
R289	0x012155
R290	0x012255
R291	0x012300
R292	0x012420
R293	0x012500
R294	0x0126F0
R295	0x012711
R296	0x012806
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C20
R301	0x012D00
R302	0x012EF0
R303	0x012F11
R304	0x013006
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013420
R309	0x013500
R310	0x0136F0
R311	0x013711
R312	0x013825
R313	0x013904
R314	0x013A18
R315	0x013B00
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x014009
R321	0x014100
R322	0x014200
R323	0x014311
R324	0x014480
R325	0x01457F
R326	0x014608
R327	0x01470A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x015F0B
R352	0x016000
R353	0x016101
R354	0x016244
R355	0x016300
R356	0x016400
R357	0x01650C
R369	0x0171AA
R370	0x017202
R371	0x017300
R372	0x017414
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x016803
R361	0x016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53

  • 0 in reply to sumathi m
    Intellectual 855 points

    Hi Ti Team,

    Could you please advice as how to go about the issue of LMK04821.

    The Board is working OK without any issues when the OSCIN is used. Where as when we use CLKIN0, we get Framer status error at the RF transceiver Board. We need to use CLKIN0 as per the design for JESD204B compliance.

    Could you please help us to understand the difference in the internal blocks to be taken care in each case, in order to get the correct output.

    Regards,

    Sumathi

  • 0 in reply to sumathi m
    TI__Mastermind 29010 points

    Hello Sumathi,

    One thing I see is that all of the SYNC_DISx bits are not set, while the SYNC_DISSYSREF bit is set. Consequently, every time you get an edge from CLKin0, all of the LMK04821 output dividers will be reset, but the internal SYSREF divider is not reset. A typical procedure would be as follows:

    1. Set all the global and local SYSREF delays, as well as the output divider delays, as desired. Note that this requires that the DDLY_PD settings for each device clock are enabled.
    2. Toggle all SYNC_DISx and SYNC_DISSYSREF to 0
    3. Send a SYNC pulse to synchronize the dividers, for example using CLKin0
    4. After synchronizing dividers, set all SYNC_DISx and SYNC_DISSYSREF to prevent divider reset
    5. Switch SYSREF_CLKin0_MUX to internal SYSREF divider, and use the re-clocked SYSREF mode in the SYSREF_MUX to re-time SYSREF pulses against the properly aligned internal SYSREF divider.

    If there are other systems that depend on the exact timing of the SYSREF pulse arriving at LMK04821 CLKin0, this approach might not work well, since the LMK04821 output pulses are re-timed by an internal divider that may not be the same phase as the input SYSREF signal. In that case the procedure could be amended as follows:

    1. Set the output divider delays as needed. Note that this requires that the DDLY_PD settings for each device clock are enabled. Power down the internal SYSREF circuitry (SYSREF_PD, SYSREF_DDLY_PD)
    2. Toggle all SYNC_DISx to 0
    3. Send a SYNC pulse to synchronize the output dividers, for example using CLKin0. The dividers will all be aligned to the falling edge of the CLKin0 or SYNC signal
    4. While CLKin0 or the SYNC source is low, and after synchronizing dividers, set all SYNC_DISx to prevent divider resets

    As far as configuring delays, TI has a few documents which can help. For example, see https://e2e.ti.com/support/clock-and-timing/f/48/p/841723/3113949, where the attached PDF includes instructions for determining the phase offset between device clock and SYSREF clock. Note that when using CLKin0 as the SYSREF source as in the second procedure above, the delay calculations should be simplified, since the only delay on CLKin0 is when CLKin0 signal is retimed to the VCO edges.

    Regards,

  • 0 in reply to Derek Payne
    Intellectual 855 points

    Hi Derek,

    Thank You for the support.

    Hope you have noted that the System is working fine with OSCIN input (122.88MHZ). The config file is attached.

    We are seeing the problem when we change the LMK input to CLKIN0 with a reference clock from CDC6208 output of 122.88MHz.

    Could you pls let me know the configuration register values with LMK04821, as wee have already tried various delay setting, but still not working.

    Could you pls share your official mail id, contact number so that we can have a conference call. we are debugging this issue from quite long time and effecting our time schedules major problem.

    Request you kind support. 

    Regards,

    Sumathi

    HexRegisterValues_22-1-2020_osc configaration.txt 
    R0 (INIT)	0x000090
R0	0x0200000E
R2	0x000200
R3	0x000306
R4	0x0004D0
R5	0x0000055B
R6	0x000600
R12	0x000C51
R13	0x000D04
R256	0x010006
R257	0x010155
R258	0x010255
R259	0x010301
R260	0x010422
R261	0x010500
R262	0x0106F0
R263	0x010711
R264	0x010806
R265	0x010955
R266	0x010A55
R267	0x010B00
R268	0x010C22
R269	0x010D00
R270	0x010EF0
R271	0x010F11
R272	0x011006
R273	0x011155
R274	0x011255
R275	0x011300
R276	0x011422
R277	0x011500
R278	0x0116F0
R279	0x011711
R280	0x011806
R281	0x011955
R282	0x011A55
R283	0x011B00
R284	0x011C22
R285	0x011D00
R286	0x011EF0
R287	0x011F11
R288	0x012006
R289	0x012155
R290	0x012255
R291	0x012300
R292	0x012422
R293	0x012500
R294	0x0126F0
R295	0x012711
R296	0x012806
R297	0x012955
R298	0x012A55
R299	0x012B00
R300	0x012C22
R301	0x012D00
R302	0x012EF0
R303	0x012F11
R304	0x00013006
R305	0x013155
R306	0x013255
R307	0x013300
R308	0x013422
R309	0x013500
R310	0x000136F0
R311	0x013711
R312	0x00013825
R313	0x013903
R314	0x013A18
R315	0x013B00
R316	0x013C00
R317	0x013D08
R318	0x013E03
R319	0x013F00
R320	0x00014009
R321	0x014100
R322	0x014200
R323	0x014351
R324	0x014493
R325	0x01457F
R326	0x014600
R327	0x0001470A
R328	0x014802
R329	0x014942
R330	0x014A02
R331	0x014B16
R332	0x014C00
R333	0x014D00
R334	0x014EC0
R335	0x00014F7F
R336	0x015003
R337	0x015102
R338	0x015200
R339	0x015300
R340	0x015478
R341	0x015500
R342	0x015678
R343	0x015700
R344	0x015896
R345	0x015900
R346	0x00015A78
R347	0x015BD4
R348	0x015C20
R349	0x015D00
R350	0x015E00
R351	0x00015F0B
R352	0x016000
R353	0x00016101
R354	0x00016244
R355	0x016300
R356	0x016400
R357	0x0001650C
R369	0x000171AA
R370	0x00017202
R371	0x017300
R372	0x017414
R380	0x017C15
R381	0x017D33
R358	0x016600
R359	0x016700
R360	0x00016803
R361	0x00016959
R362	0x016A20
R363	0x016B00
R364	0x016C00
R365	0x016D00
R366	0x016E13
R8189	0x1FFD00
R8190	0x1FFE00
R8191	0x1FFF53