CDCE913: Absolute Maximum Ratings for SCL/S2 and SDA/S1 pins II

Hello,

According to following E2E thread, even though SCL and SDA are 3.3V tolerant, it is not recommended to drive the input when VDD = 0V.

https://e2e.ti.com/support/clock-and-timing/f/48/p/769394/2845927?tisearch=e2e-sitesearch&keymatch=CDCE913#2845927

My customer does not directly drive SCL and SDA with 3.3V level, would like to pull up them to 3.3V via 1kohms resister.

In this case, the 3.3V pull up rail can power up when VDD = 0V?

Best regards,

K.Hirano