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LMX2594: Effect of PFD frequency and fractional divider on LMX2594 clock jitter

Part Number: LMX2594
Other Parts Discussed in Thread: DAC38RF82, , DAC38RF82EVM, LMK04832

Hi,

We have product which uses LMX2594 as the on-board clock source for the DAC38RF82 on it. One of our customers has reported a problem where a CW tone output from the DAC38RF82 has significant jitter when the fractional part of LMX2594 is used (e.g. a sample rate of 5529.6 MHz). This problem goes away when using an external clock source (e.g. a signal generator) or when the fractional part is not used (e.g. a sample rate of 3200 MHz).

Is this behaviour expected? Are there any software settings available in the LMX2594 to improve the output jitter?

I can attach some plots and register settings from my tests, if it will help with your analysis. I also have the LMX2594EVM and DAC38RF82EVM in case you would like me to perform an experiment using those instead of our board.

Thanks,
Ayush

  • Hi Ayush,

    Yes, please provide a TICS Pro configuration file for us to review, thanks.

  • Hi Noel,

    Thanks for looking into this. I have attached three sets of register settings - 1382.4 MHz, 1575.936 MHz and 3200.00 MHz. In all cases the OSCin frequency is 100 MHz. Among these, we have observed problems with the first two.

    Our setup involves an LMX2594 (or an external coax input) as the clock source, followed by LMK04832 as the clock distributor, with the final output reaching DAC38RF82. Because of limitations in the LMK, we utilize the DACPLL in DAC38RF82 to create sample rates higher than 3200 MHz. For example, the 1382.4 MHz input is used to produce a DAC sample clock of 5529.6 MHz. Similarly, the 1575.936 MHz input is used to create 6303.744 MHz. The OSCin input of LMX2594 is driven by Si571 VCXO, which is phase locked to an external 10 MHz reference using LMK04832's PLL1. The VCOs and PLL2 on the LMK04832 are left unused.

    We have ruled out issues with PLLs in LMK04832 or DAC38RF82 because using an external clock instead of the LMX2594 solves the problem. The problem manifests as difficulty in demodulating a QPSK signal output from the DAC38RF82 because the constellation 'breathes' as the phase jitters and symbols get mixed up. The receiver/demodulator has been verified by using it to demodulate QPSK signal from a R&S SMIQ-03B generator. Even with a CW tone output from the DAC38RF82 we can see the phase change when we digitize it on the receiver side.

    Thanks,
    Ayush

    LMX2594_3200MHz.txt
    R112	0x700000
    R111	0x6F0000
    R110	0x6E0000
    R109	0x6D0000
    R108	0x6C0000
    R107	0x6B0000
    R106	0x6A0000
    R105	0x690021
    R104	0x680000
    R103	0x670000
    R102	0x663F80
    R101	0x650011
    R100	0x640000
    R99	0x630000
    R98	0x620200
    R97	0x610888
    R96	0x600000
    R95	0x5F0000
    R94	0x5E0000
    R93	0x5D0000
    R92	0x5C0000
    R91	0x5B0000
    R90	0x5A0000
    R89	0x590000
    R88	0x580000
    R87	0x570000
    R86	0x560000
    R85	0x55D300
    R84	0x540001
    R83	0x530000
    R82	0x521E00
    R81	0x510000
    R80	0x506666
    R79	0x4F0026
    R78	0x4E0003
    R77	0x4D0000
    R76	0x4C000C
    R75	0x4B0840
    R74	0x4A0000
    R73	0x49003F
    R72	0x480006
    R71	0x470081
    R70	0x46C350
    R69	0x450000
    R68	0x4403E8
    R67	0x430000
    R66	0x4201F4
    R65	0x410000
    R64	0x401388
    R63	0x3F0000
    R62	0x3E0322
    R61	0x3D00A8
    R60	0x3C0000
    R59	0x3B0001
    R58	0x3A8001
    R57	0x390020
    R56	0x380000
    R55	0x370000
    R54	0x360000
    R53	0x350000
    R52	0x340820
    R51	0x330080
    R50	0x320000
    R49	0x314180
    R48	0x300300
    R47	0x2F0300
    R46	0x2E07FC
    R45	0x2DC0C0
    R44	0x2C1FA3
    R43	0x2B0000
    R42	0x2A0000
    R41	0x290000
    R40	0x280000
    R39	0x278CA0
    R38	0x260000
    R37	0x250204
    R36	0x240500
    R35	0x230004
    R34	0x220000
    R33	0x211E21
    R32	0x200393
    R31	0x1F43EC
    R30	0x1E318C
    R29	0x1D318C
    R28	0x1C0488
    R27	0x1B0002
    R26	0x1A0DB0
    R25	0x190624
    R24	0x18071A
    R23	0x17007C
    R22	0x160001
    R21	0x150401
    R20	0x14B048
    R19	0x1327B7
    R18	0x120064
    R17	0x11012C
    R16	0x100080
    R15	0x0F064F
    R14	0x0E1E70
    R13	0x0D4000
    R12	0x0C5001
    R11	0x0B00A8
    R10	0x0A10D8
    R9	0x090604
    R8	0x082000
    R7	0x0740B2
    R6	0x06C802
    R5	0x0500C8
    R4	0x040A43
    R3	0x030642
    R2	0x020500
    R1	0x010808
    R0	0x00241C
    

    LMX2594_1575.936MHz.txt
    R112	0x700000
    R111	0x6F0000
    R110	0x6E0000
    R109	0x6D0000
    R108	0x6C0000
    R107	0x6B0000
    R106	0x6A0000
    R105	0x690021
    R104	0x680000
    R103	0x670000
    R102	0x663F80
    R101	0x650011
    R100	0x640000
    R99	0x630000
    R98	0x620200
    R97	0x610888
    R96	0x600000
    R95	0x5F0000
    R94	0x5E0000
    R93	0x5D0000
    R92	0x5C0000
    R91	0x5B0000
    R90	0x5A0000
    R89	0x590000
    R88	0x580000
    R87	0x570000
    R86	0x560000
    R85	0x55D300
    R84	0x540001
    R83	0x530000
    R82	0x521E00
    R81	0x510000
    R80	0x506666
    R79	0x4F0026
    R78	0x4E0003
    R77	0x4D0000
    R76	0x4C000C
    R75	0x4B0880
    R74	0x4A0000
    R73	0x49003F
    R72	0x480006
    R71	0x470081
    R70	0x46C350
    R69	0x450000
    R68	0x4403E8
    R67	0x430000
    R66	0x4201F4
    R65	0x410000
    R64	0x401388
    R63	0x3F0000
    R62	0x3E0322
    R61	0x3D00A8
    R60	0x3C0000
    R59	0x3B0001
    R58	0x3A8001
    R57	0x390020
    R56	0x380000
    R55	0x370000
    R54	0x360000
    R53	0x350000
    R52	0x340820
    R51	0x330080
    R50	0x320000
    R49	0x314180
    R48	0x300300
    R47	0x2F0300
    R46	0x2E07FC
    R45	0x2DC0C0
    R44	0x2C1FA3
    R43	0x2B4EFA
    R42	0x2A0000
    R41	0x290000
    R40	0x280000
    R39	0x278CA0
    R38	0x260000
    R37	0x250104
    R36	0x2403B1
    R35	0x230004
    R34	0x220000
    R33	0x211E21
    R32	0x200393
    R31	0x1F43EC
    R30	0x1E318C
    R29	0x1D318C
    R28	0x1C0488
    R27	0x1B0002
    R26	0x1A0DB0
    R25	0x190624
    R24	0x18071A
    R23	0x17007C
    R22	0x160001
    R21	0x150401
    R20	0x14B048
    R19	0x1327B7
    R18	0x120064
    R17	0x11012C
    R16	0x100080
    R15	0x0F064F
    R14	0x0E1E70
    R13	0x0D4000
    R12	0x0C5001
    R11	0x0B00A8
    R10	0x0A10D8
    R9	0x090604
    R8	0x082000
    R7	0x0740B2
    R6	0x06C802
    R5	0x0500C8
    R4	0x040A43
    R3	0x030642
    R2	0x020500
    R1	0x010808
    R0	0x00241C
    

    LMX2594_1382.4MHz.txt
    R112	0x700000
    R111	0x6F0000
    R110	0x6E0000
    R109	0x6D0000
    R108	0x6C0000
    R107	0x6B0000
    R106	0x6A0000
    R105	0x690021
    R104	0x680000
    R103	0x670000
    R102	0x663F80
    R101	0x650011
    R100	0x640000
    R99	0x630000
    R98	0x620200
    R97	0x610888
    R96	0x600000
    R95	0x5F0000
    R94	0x5E0000
    R93	0x5D0000
    R92	0x5C0000
    R91	0x5B0000
    R90	0x5A0000
    R89	0x590000
    R88	0x580000
    R87	0x570000
    R86	0x560000
    R85	0x55D300
    R84	0x540001
    R83	0x530000
    R82	0x521E00
    R81	0x510000
    R80	0x506666
    R79	0x4F0026
    R78	0x4E0003
    R77	0x4D0000
    R76	0x4C000C
    R75	0x4B0880
    R74	0x4A0000
    R73	0x49003F
    R72	0x480006
    R71	0x470081
    R70	0x46C350
    R69	0x450000
    R68	0x4403E8
    R67	0x430000
    R66	0x4201F4
    R65	0x410000
    R64	0x401388
    R63	0x3F0000
    R62	0x3E0322
    R61	0x3D00A8
    R60	0x3C0000
    R59	0x3B0001
    R58	0x3A8001
    R57	0x390020
    R56	0x380000
    R55	0x370000
    R54	0x360000
    R53	0x350000
    R52	0x340820
    R51	0x330080
    R50	0x320000
    R49	0x314180
    R48	0x300300
    R47	0x2F0300
    R46	0x2E07FC
    R45	0x2DC0C0
    R44	0x2C1FA3
    R43	0x2B3DE0
    R42	0x2A0000
    R41	0x290000
    R40	0x280000
    R39	0x278CA0
    R38	0x260000
    R37	0x250104
    R36	0x24033D
    R35	0x230004
    R34	0x220000
    R33	0x211E21
    R32	0x200393
    R31	0x1F43EC
    R30	0x1E318C
    R29	0x1D318C
    R28	0x1C0488
    R27	0x1B0002
    R26	0x1A0DB0
    R25	0x190624
    R24	0x18071A
    R23	0x17007C
    R22	0x160001
    R21	0x150401
    R20	0x14B048
    R19	0x1327B7
    R18	0x120064
    R17	0x11012C
    R16	0x100080
    R15	0x0F064F
    R14	0x0E1E70
    R13	0x0D4000
    R12	0x0C5001
    R11	0x0B00A8
    R10	0x0A10D8
    R9	0x090604
    R8	0x082000
    R7	0x0740B2
    R6	0x06C802
    R5	0x0500C8
    R4	0x040A43
    R3	0x030642
    R2	0x020500
    R1	0x010808
    R0	0x00241C
    

  • Hi Ayush,

    I checked the _1382.4MHz txt file and I see the following issues:

    1. The reference clock is 100MHz, what is the reason for make the fpd = 10MHz? This will make N divider very big and therefore increase PLL noise

    2. Another problem with very low fpd is, in fractional channel, the phase noise at far end will be bad. You may see a bump over there. This bump does not exist in integer channel. 

    3. PFD_DLY_SEL is not set properly. Please set it to the suggested value as shown in Table 2 in the datasheet.

    4. This is a fractional channel and there is an expected fractional spurs at 400kHz offset. If your loop bandwidth is less than 100kHz, it is fine, but if you want to have a wide loop bandwidth, this spurs will become obvious. One way to remove this spurs is to set the fractional DEN to 3600001. The output frequency will not be exact (i.e. output freq = 1382.3999979MHz) but I don't think this is matter.

    In conclusion, I suggest: (1) make the fpd wider, say 100MHz. (2) Set PFD_DLY_SEL according to datasheet Table 2. (3) Set DEN=3600001.

  • Hi Noel,

    Thanks for the suggestions. I am sorry for not getting back to you sooner. I am tied up in other tasks for the next two weeks and the virus outbreak might force me to stay home in the near future. I can focus on this task after that.

    1. I have found that reducing the PFD frequency helps me get to where I want to be. For example, with a 10 MHz PFD frequency, I see poor phase stability when the sample rate for DAC38RF82 is 6303.744 MHz off of a 1575.936 MHz output from LMX2594. Here's the video of the QPSK demod in this situation -

    drive.google.com/open

    When I change the sample rate to 6303.74 MHz off of 1575.935 MHz, I see good phase stability -

    drive.google.com/open

    By reducing the PFD frequency to 1 MHz, I can get the 6303.744 MHz sample rate to work as well. this is shown in the following video -

    drive.google.com/open

    This is contrary to established theory and your suggestion but I haven't found any other way to make the hardware work properly. Can you think of any reason why this would be so?


    2. When you say far end, how far from the fundamental would this be?


    3. I did find and fix the PFD_DLY_SEL problem. It was being calculated based on the wrong (local) variable for Modulator Order. I haven't gone back to run my QPSK test after this change though.

    Can you explain the method for selecting the best MASH_ORDER? For example, if the fractional numerator is 0, should the MASH_ORDER be 0 (Integer) for best performance? What about fractional modes?

    My understanding is that this needs to be set based on the order of the loop filter. I scanned through AN-1879 (Fractional N Frequency Synthesis) and the plots are very helpful, but I did not find a clear guideline for selecting modulator order.


    4. We do notice these spurs but they are not significant enough problem for us. Phase stability is far more important for the symbol recovery application. The point about changing the DEN to 3600001 is very good. I will definitely try it. I am not sure if the frequency offset will cause problems on the receiver side.


    Thanks again for your continued support, it has been very helpful. I am not able to fully devote myself to this problem right now but I will be able to answer questions and run quick tests.

  • Hi Ayush,

    1. The problem is due to frequency error and phase noise

    In configuration A, this is your original configuration with fpd=10MHz, the output frequency is off by 18.5Hz. Your DAC will be off by 4 x 18.5 = 74Hz. Second issue with this configuration is the phase noise may be bad because of the phase noise bump I mentioned before.

    in configuration B, the output frequency is exact, there is no freq error and I believe there will be no phase noise bump as well. fpd remains unchanged at 10MHz.

    In configuration C, fpd = 1MHz, as a result, you can get exact 1575.936MHz output. 

    If configuration C is already good enough to you, OK, use this configuration. If you want to get better phase noise, you can get exact frequency output with  fpd = 100MHz.

  • Hi Noel,

    Thanks for the clarification. You are right, with 100 MHz PFD frequency I can get a stable output.

    Can you please also elaborate on the choice of MASH_ORDER?

    Thanks,
    Ayush

  • Hi Ayush,

    For an integer channel, you can set MASH_ORDER to any value.

    With a fractional channel, you cannot make MASH_ORDER = 0, otherwise the fraction will be ignored. 

    If your application has mixed integer and fractional channels, I recommend make MASH_ORDER = 0x3 = 3rd order. 

    4th order is usually not required. In some cases, a 2nd order MASH may return better phase noise but higher spurs than with a 3rd order MASH. In short, we have to experiment with the MASH_ORDER setting, but in general, I see 3rd order is good enough for most of the cases.

  • Hi Noel,

    Thanks a lot for the detailed response. This gives me a better understanding of the part. I appreciate all your help.

    Ayush