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LMX2531: Ftest/LD pin OUTPUT TYPE at cold start

Kazuhiko Hirano
Genius 11613 points
Part Number: LMX2531

Hello,

 

At cold start, after all VCCDIG, VCCVCO, VCCBUF, VCCPLL and CE get 3.3V and before the initialization sequence (1st R5 INIT 1 access), what OUTPUT TYPE could Ftest/LD pin be in the table 11 of the datasheet?

Is the OUTPUT TYPE deterministic or could be any of in the table 11?

 

My customer is observing Ftest/LD pin is sometime high, sometimes low or sometimes intermediate low voltage probably affected by a connected FPGA.

 

Best regards,

 

K.Hirano

  • 0
    TI__Genius 11613 points

    Hello,

     

    I mentioned Vcc and LD get 3.3V, it was wrong.

     

    It shoulda been 3.0V by right.

     

    Best regards,

     

    K.Hirano

  • 0 in reply to Kazuhiko Hirano
    TI__Guru* 81360 points

    Hi Hirano-san,

    After Vcc power up, if the internal registers get POR successfully, the LD pin is silicon default to disable. 

    Is the LD pin status deterministic after Vcc power up at room temperature? What is the status if a RESET (first R5 INIT) is applied?

  • 0 in reply to Noel Fung
    TI__Genius 11613 points

    Noel,

     

    Thank you for your response.

     

    No, just after Vcc power up but before the 1st R5 INIT, the LD pin status is not deterministic at my customer.

    However, after the 1st R5 INIT, LD pin gets low and gets high when PLL is locked.

     

    My customer would just like to know if the status of the LD pin is deterministic before the 1st R5 INIT or not.

    So your answer seems that it is not deterministic and could be anything in the table 11 in the datasheet.

    Is my understanding correct?

     

    Best regards,

     

    K.Hirano

  • 0 in reply to Kazuhiko Hirano
    TI__Guru* 81360 points

    Hi Hirano-san,

    Right, looks like the POR was not successful, so after Vcc power up, the LD status was not deterministic. We can ignore the pin status before the first R5 INIT.