LMK04828: LMK04828 modes of operation

Hello Ayesha,

1. Configuration 2 is supported. Clock and SYSREF dividers are supplied from the clock distribution path, which can be either the VCOs or Fin. Clock divider can also be set to 1 (if duty cycle correction is enabled) or the divider/digital delay blocks can be bypassed entirely, if needed. Note that if you plan to use 3GHz output, the amplitude of provided clock output formats will be attenuated at high frequency; the LMK04832 also meets your requirements for Configuration 2, is p2p compatible with LMK04828, and includes a CML output format in bypass mode to maintain reasonable output amplitude at high frequency.
2. Fin pin can accept up to 3.1GHz.
3. Yes, Fin supports 50Ω source sine wave input. You will need to terminate with an external 50Ω resistor just before the AC-coupling capacitor (Fin pin self-biases, and 50Ω would affect biasing). Make sure to set CLKIN1_TYPE register to "bipolar" mode and AC-couple the input through 0.1µF. The unused pin in the differential pair should be connected by 0.1µF to GND. Single-ended Fin pin voltage should not exceed 2Vpp, and slew rate should be > 0.5V/ns (sine wave slew rate = 2π*Fin*Vpk, e.g. for a 3GHz 200mVpp signal 2π * 3GHz * (0.2Vpp/2) = 1.8V/ns
4. Yes, in distribution mode the internal VCOs and PLLs can be disabled to minimize spurious coupling. In the TICS Pro software GUI for the LMK04828, there is a "Set Modes" page which you can use to setup distribution mode, and which shows the various blocks which can be powered down. At a minimum, this includes PLL1_PD, PLL2_PD, PLL2_PRE_PD, VCO_PD, and VCO_LDO_PD

Regards,

Hello Ayesha,

Note that CLKin2/OSCout initializes in OSCout LVPECL mode. To avoid the situation where OSCout is backdriving the SPDT switch, just make sure there is no emitter resistor biasing on OSCout, and the driver will be unable to drive anything on startup. Then after POR, change OSCout to CLKin2 and there should be no additional work required.

Bipolar mode can be used with sine wave input. But for 10 MHz sine wave, due to the low frequency, you may have trouble getting an acceptable slew rate. 2π*10MHz*1Vpk = 0.06V/ns, whereas datasheet minimum recommended slew rate is 0.1V/ns. Clipped sine or LVCMOS can work better for 10 MHz, since the slew rate can be improved greatly without exceeding Vpp limits. In bipolar mode, make sure to limit the Vpp amplitude to 2.4V on CLKin0 and CLKin2. CLKin1 in bipolar mode should be limited to 2.4Vpp if used as an input to PLL1, or to 2Vpp if used as Fin.

For the TCXO on CLKin0, if the amplitude is expected to be the full 3.3V LVCMOS range, you should instead configure the CLKIN0_TYPE for MOS mode and use a DC-coupled input. The datasheet specifies the single-ended MOS mode voltage level can be anywhere between 0V and VCC. For CLKin2, an additional stage to get clipped sine, or a transformation to LVCMOS, may be needed to keep the slew rate above 0.1V/ns.

Regards,