Hello,
I am trying to program the LMH1983 to genlock to a User Defined Format, but I have not succeeded.
I need the LMH1983 to genlock to an NTSC, 525I, but I not want to provide the Field, and the Vsync signals. Therefore, I need to configure the part to look at Hsync.
Here are the Input Timing Parameters based on Table 2: Supported Formats Table LUT.
Format: NTSC, 525I
Reference Divider: 1
Feedback Divider: 1716
Phase Detector Freq: 15.7343kHz
PD Period per Frame Counter: 525
PLL: 1
PLL Clock Freq: 27.0MHz
Total Clocks per Line Counter: 1716
Total Lines Per Frame: 525
Frame Rate: 29.97Hz
I do not know, if I have to, how to set the registers highlighted in red. Can someone explain to me how to exactly set these registers?
| LMH1983 Register |
Resgister Desc | Resgister Val | Comments |
| 0x05 | Device Control | 0x80 | |
| 0x05 | Device Control | 0x09 | |
| 0x06 | Input Polarity | 0x00 | |
| 0x0A | Output Buffer Control | 0xEE | |
| 0x0B | Output Frame Control - Offset1_MSB | ? | |
| 0x0C | Output Frame Control - Offset1_LSB | ? | |
| 0x11 | Alignment Control – TOF1 | 0x38 | |
| 0x20 | Input Format | 0x00 | |
| 0x21 | Output Frame Lookup - Input Vsync Code | 0x03 | |
| 0x25 | PLL1 Advanced Control | 0X05 | |
| 0x29 | PLL1 Advanced Control R Counter MSB | ? | |
| 0x2A | PLL1 Advanced Control R Counter LSB | ? | |
| 0x2B | PLL1 Advanced Control N Counter MSB | ? | |
| 0x2C | PLL1 Advanced Control N Counter LSB | ? | |
| 0x51 | User Auto Format -27M High Value MSB | 0X86 | There are 34320 clock cycles in 20 Hsync lines The High Value is 34322. The Low Value is 34318. Not sure if this is corect. +/- two clocks |
| 0x52 | User Auto Format -27M High Value LSB | 0X12 | |
| 0x53 | User Auto Format -27M Low Value MSB | 0X86 | |
| 0x54 | User Auto Format -27M Low Value LSB | 0X0E | |
| 0x5A | User Auto Format - LPF MSB | 0X02 | Lines per Frame |
| 0x5B | User Auto Format - LPF LSB | 0X0D | |
| 0x5D | User Auto Format Misc | 0x13 |
Thanks,
Aris Araujo
