LMK04821: Trouble syncronizing multiple parts - SYNC_DISSYSREF strange behavior

Hi Jay,

SYNC (a.k.a. divider reset) and SYSREF share a path in the LMK0482x. Think of SYNC_DISSYSREF as an AND-gate signal between the shared SYNC/SYSREF distribution path and the SYSREF divider reset line. So when you disable SYNC_DISSYSREF, you're enabling the path to the SYSREF divider reset. If you don't also arrange for the SYNC signal to be the common reset between the dividers, the SYSREF pulser will be sent out over the shared SYNC/SYSREF distribution path instead, and the SYSREF pulser will be its own reset signal. Basically, you're SYNCing yourself in the foot.

One thing to note about zero-delay mode is that, unless the phase detector of the ZDM PLL is equal to the greatest common divisor GCD(input frequencies, output frequencies), there could potentially be many more phases for lower-frequency clocks. In your tcs file, I see the SYSREF is 9.375 MHz, whereas the phase detector is 10 MHz. Since there's a beat frequency between 9.375 MHz and 10 MHz, there's least common multiple LCM(9.375, 10) / MIN(9.375, 10) = 150 / 9.375 = 16 different possible phase alignments for the SYSREF dividers against the 10 MHz reference, and LCM(9.375, 100) / MIN(9.375, 100) = 300 / 9.375 = 32 different possible phase alignments for the SYSREF dividers against the 100 MHz reference.

If you want to ensure the SYSREF dividers are also aligned without needing to issue a SYNC event, your ZDM phase detector rate must be GCD(100 MHz, 10 MHz, 9.375 MHz) = 625 kHz, or some integer divide of 625 kHz. Otherwise you will need to use a SYNC event to tell the SYSREF dividers when to start counting.

For more information about synchronizing multiple LMK0482x devices, please see the Multi-SYNC app note and accompanying graphical presentation: 

• http://www.ti.com/lit/an/snaa294/snaa294.pdf app note
• https://e2e.ti.com/support/clock-and-timing/f/48/p/841723/3113949 presentation

Regards,