We've been using the LMH1983 for over more than a decade already to genlock our HD- and 3G-SDI cameras to an external source. Lately we have been informed by a customer that a small number of cameras show problems with PLL1 and/or TOF1 lock status.
Upon investigation, we found out that we had configured the PLL1 Advanced Control register wrong. Although the VCXO we use is connected like in 8.2 Functional Block Diagram (so a Single Ended clock), we mistakenly configured the clock in register 0x25 as 0x05 instead of 0x01 (Bit2: 1 = Differential instead of 0 = Single Ended). Preliminary tests show that cameras that previously failed with the incorrect clock setting work correctly when switched to the proper clock setting.
We're wondering now, what happens when the clock is switched over from Differential to Single Ended. Externally we have found no difference, the amplitude of the VCXO clock applied doesn't change. But what happens internally in the LMH1983 that could explain this. If a Single Ended clock (full 3.3V swing) is applied to XOin+ and XOin- is kept at 1.65V, but the input mode is set to Differential. could this explain locking problems? Or are we just (un)lucky that correcting the input mode seems to fix the locking problems and we really should be looking further? Note that the majority of the cameras doesn't seem to be bothered by the wrong clock setting.