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LMH1983: Wrong clock configuration for VCXO clock signal for PLL1

Part Number: LMH1983

We've been using the LMH1983 for over more than a decade already to genlock our HD- and 3G-SDI cameras to an external source. Lately we have been informed by a customer that a small number of cameras show problems with PLL1 and/or TOF1 lock status.

Upon investigation, we found out that we had configured the PLL1 Advanced Control register wrong. Although the VCXO we use is connected like in 8.2 Functional Block Diagram (so a Single Ended clock), we mistakenly configured the clock in register 0x25 as 0x05 instead of 0x01 (Bit2: 1 = Differential instead of 0 = Single Ended). Preliminary tests show that cameras that previously failed with the incorrect clock setting work correctly when switched to the proper clock setting.

We're wondering now, what happens when the clock is switched over from Differential to Single Ended. Externally we have found no difference, the amplitude of the VCXO clock applied doesn't change. But what happens internally in the LMH1983 that could explain this. If a Single Ended clock (full 3.3V swing) is applied to XOin+ and XOin- is kept at 1.65V, but the input mode is set to Differential. could this explain locking problems? Or are we just (un)lucky that correcting the input mode seems to fix the locking problems and we really should be looking further? Note that the majority of the cameras doesn't seem to be bothered by the wrong clock setting.

  • Hello, 

    So the device was programmed to the incorrect condition, differential when a single ended clock was provided. If the register is not programmed the device will automatically distinguish between a single ended or differential signal, but by forcing it to incorrect mode this may have caused the problem. 

    The note on providing single ended 3.3V swing on XOin+ and holding XOin- at 1.65 and setting it to differential, this would violate the vcm and swing specs provided in datasheet so it would cause problems. 

    Regards, Amin 

  • Hello Amin,

    We already knew that we violate the specification here (and will correct this), but the question remains, what happens internally that may cause sporadic issues with the PLL1 falling out of lock? We only see this happening for a small proportion of cameras and we will have a hard time explaining to our customer that we will need to update the firmware of the cameras to fix this, if we can't explain why.

    I'm also surprised the type of clock is autodetected, the specification doesn't mention this anywhere.

    Regards, Arjen

  • Hi Arjen, 

    Perhaps this was at an edge condition, which caused the sporadic behavior and not a widespread issue. Bottom line since this is beyond the spec and this is a fairly older part with the designers no longer with TI to discuss this hypothetical with, we're not at a place to divulge the specific details into the fail mechanism. 

    Thanks and regards, 

    Amin