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Part Number: LMK04826
i'm working on a design with 4 ADS52J90 and a Intel Arria 10 fpga. The ADS52J90 requires a 40MHz clk in our setup and the Intel JESD204B IP block requires 160MHz. We wnt to use sysref for synchronization between the devices. With the clockdesigntool I can not get this configuration working.
Can these clocks be made with the LMK04286 that is used on the ADS52J90 EVM? I would like to use this device to reuse the software developed for the devkit.
What would be the best input clock frequency to use in our setup?
Apologies for the delay. If 40MHz is the main clock to ADS52J90, and the SYSREF is lower frequency, the LMK04826 cannot be used without an external VCO. This is because the maximum clock divide is 32: 40MHz * 32 = 1280MHz, while the minimum VCO frequency is 1840MHz. I also checked the LMK04821 (which has a post-divider to reduce the VCO frequency, the only register difference from LMK04826), but the LMK04821 has a frequency hole at 160 MHz.
In theory you could use the p2p-compatible LMK04832, which has 10-bit dividers. With the LMK04832 you could set the VCO frequency to 3200MHz and divide by 20 and 80 to get 160MHz and 40MHz. Unfortunately in addition to requiring rework, the register programming would need to be updated manually through TICS Pro. If I recall correctly, the software built for the ADS52J90EVM allows users to load their own firmware, so although the ADS52J90EVM GUI might not display the right values and could not be used to update most registers in real-time, you would still be able to load a firmware image to the LMK04832 by generating it first using TICS Pro, and the SYNC pulses or SYSREF requests generated by the ADS52J90EVM software would still be handled identically to the LMK04826 case.
Regarding the selection of input frequency, you would need to talk to the ADS52J90EVM team to determine their typical system configuration and synchronization procedure for the LMK04826 case, and then generate a comparable configuration for the LMK04832. The "best" input frequency depends on a few factors, including the available frequency range, whether zero-delay mode is used, and whether PLL1 is used as a jitter cleaner. I can help with input frequency selection later, if you decide using the LMK04832 for evaluation is an acceptable amount of effort.
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In reply to Derek Payne:
The only way to get the right clocks will be to switch to the LMK04832. So that is what we will do. Can you help me with the best configuration for the LMK04832 for our use case?
In reply to Michel Wouters:
I want to make sure I understand what you're planning to do: Are you testing this with our own schematic and layout, or are you reworking an EVM and checking the results in the single-device case first?
I briefly reviewed the ADS52J90EVM configuration files for the LMK04826, and it looks like the EVM GUI software is somewhat inconsistent about its LMK usage - in some cases the device is placed in distribution mode, in other cases the onboard PLLs and oscillators are used, with no clear reasoning for the choices. The GUI software also makes some questionable choices, including in some cases leaving both PLLs active despite placing the clock in distribution mode, or leaving the SYSREF in continuous mode on clocks adjacent to the ADC clock (which adds a spur at the SYSREF frequency). Aside from the FPGA synchronizing the clock outputs or making SYSREF requests, I'm not sure what advantage the ADS52J90EVM software has for you.
Are you planning to use the LMK04832 PLLs, or just the distribution mode? For comparison:
We have an EVM and are using that to see if we can get things up and running with a single lane case. We also have a EVM with our FPGA and are developing the VHDL for this to get things up and running. So we will not be using the EVM software in our final design. So lets forget the EVM and focus on our final with our own schematic and layout. That is the use case I mentioned earlier with 4 ADCs and 1 FPGA. And we will program the settings for the LMK device with the FPGA through the SPI interface.
My preference is the second suggestion you do:
A clean 100MHz oscillator with PLL2 active is sufficient to generate the required 160MHz and 40MHz output clocks. The VCO for PLL2 would be set to 3200MHz. Conceivably there are other input frequency choices but they may be expensive or rare; 100MHz is an easy and well-stocked value carried by many vendors.
We want to use a pulsed SYSREF as we do not want spurs from the SYSREF in our system. PLL1 can be switched off.
What pitfalls should I watch out for with the rest of the configuration for the LMK04832?
Michel Wouters So we will not be using the EVM software in our final design.
Keep in mind, you will probably using the TICS Pro EVM software for LMK04832 to create the configuration. You can then export it as a .txt file to get the raw registers your FPGA will program.
Also, as per the datasheet section 8.3.3 where it talks about the proper procedure for enabling SYSREF, the LMK04832 GUI has a Frequency Planner tab. The frequency planner tab is a bit more than just frequency planner, because it will also help configure things like general device mode and SYSREF.
Now that you know the route you want to take, single PLL with 100 MHz OSCin reference, please take a look at this frequency planner / part configuration in the LMK04832 GUI to see if that helps configure your device for you. It also should optimize assignment to the output for crosstalk purposes.
Let me know if the software gives you any troubles or if you have any recommendations for improvement of the frequency planner. - I did notice in INPUT REFERENCE, it's not terribly clear about the Clock type. MOS is used for LVCMOS inputs on CLKin. Otherwise Bipolar is your option. (No option for OSCin input actually).
One other note to keep in mind: CLKin0 has a dual purpose for synchronization input and CLKin1 has a dual purpose as distribution input, CLKin2 has dual purpose as OSCout. All can be used as a reference to PLL2 with a small in-band phase noise hit (0.5 db or less from memory?) vs OSCin.
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