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LMK05028: 10MHz output from 1PPS ref

michele pedroni
Prodigy 180 points
Part Number: LMK05028

Hi,

I'm trying to configure LMK05028 to generate a 10MHz output from a 1PPS reference signal coming from a GPS receiver. The configuratio is the following:

XO: 48MHz

TCXO: 10MHz

IN0: 1PPS

OUT0: 10MHz from DPLL2

DPLL2 Mode: 3-loop

I attached the .tcs file in order to let you have a deeper look to my configuration.

On OUT0, I get 10,000,003MHz rather than 10,000,000MHz; after some tests, it seems that the component do not correctly locks to the 1PPS input: infact, the 10,000,003MHz output is present even if the GPS receiver is not connected.

What would you suggest to solve the problem?

Best Regards,

Michele

1PPS_LMK05028.tcs

  • 0
    TI__Expert 6140 points

    Hello Michele, 

    Is the status readback already in the .tcs file? It doesn't seem to be the case considering the information you have provided and what's it's showing there.. 

    Please go to status tab and do a readback. 

    Thanks and regards,

    Amin

  • 0 in reply to Amin Eshraghi
    Prodigy 180 points

    Hello Amin,

    the component is not directly connected to the PC, but it is already installed on our custom CPU board and configured through I2C: from TICS PRO, we generate 2 configuration files with "Save DPLL1 Register Set with Outputs" and "Save DPLL2 Register Set with Outputs" respectively and we use them as an input for our configuration script. For this reason, a read back from TICS PRO may nnot reflect the actual component configuration.

    Anyway, I attach you the following files:

    DPLL1_v025.txt & DPLL2_v025.txt --> configuration files from TICS PRO

    HexRegisterValues.txt --> Register read back from TICS PRO (offline mode)

    readback.txt --> Read back from LMK05028 through I2C

    Hope this helps to have a closer look to the problem.

    Regards,

    Michele

    DPLL1_v025.txt 
    # First power down the outputs changing
R51	0x00333e	 &	 0x00003e

# APLL1/DPLL1 Registers
R90	0x005a03
R91	0x005b03
R92	0x005c33
R93	0x005d0f
R94	0x005e17
R95	0x005f05
R102	0x006600
R103	0x006732
R104	0x006800
R105	0x006900
R106	0x006a00
R107	0x006b00
R108	0x006c00
R109	0x006d03
R110	0x006e00
R111	0x006f01
R112	0x007000
R113	0x007100
R114	0x007200
R115	0x007300
R116	0x007400
R117	0x007500
R118	0x0076ff
R119	0x0077ff
R120	0x0078ff
R121	0x0079ff
R122	0x007aff
R123	0x007b02
R124	0x007c02
R125	0x007d00
R126	0x007e01
R127	0x007f01
R128	0x008077
R158	0x009e03
R159	0x009f0d
R160	0x00a029
R295	0x012700
R296	0x012803
R302	0x012e2f
R303	0x012f0a
R304	0x013000
R305	0x013100
R306	0x013200
R307	0x013301
R308	0x013400
R309	0x013500
R310	0x013600
R311	0x013700
R312	0x013800
R313	0x013900
R314	0x013a00
R315	0x013b00
R316	0x013c00
R317	0x013d00
R318	0x013e06
R319	0x013f8b
R320	0x014000
R321	0x014100
R322	0x014200
R323	0x014361
R324	0x0144a8
R325	0x0145a0
R326	0x014604
R327	0x014700
R328	0x014803
R329	0x014984
R330	0x014a00
R331	0x014b00
R332	0x014c00
R333	0x014d1c
R334	0x014e00
R335	0x014f00
R336	0x015002
R337	0x015100
R338	0x015200
R339	0x015301
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x0159e0
R346	0x015a00
R347	0x015ba1
R348	0x015c03
R349	0x015d01
R350	0x015e09
R351	0x015f01
R352	0x016000
R353	0x01612c
R354	0x01620f
R355	0x016302
R356	0x016406
R357	0x016501
R358	0x016600
R359	0x01670e
R360	0x016818
R361	0x016902
R362	0x016a0f
R363	0x016b04
R364	0x016c35
R365	0x016d17
R366	0x016e4b
R367	0x016f4b
R368	0x01704b
R369	0x01714b
R370	0x01724b
R371	0x01734b
R372	0x0174ff
R373	0x0175ff
R374	0x0176ff
R375	0x0177ff
R376	0x0178ff
R377	0x017924
R378	0x017a00
R379	0x017b64
R380	0x017c00
R381	0x017d00
R382	0x017e00
R383	0x017f01
R384	0x018005
R385	0x0181f5
R386	0x0182e1
R387	0x018300
R388	0x018400
R389	0x01856e
R390	0x018600
R391	0x018700
R392	0x018800
R393	0x018901
R394	0x018a05
R395	0x018bf5
R396	0x018ce1
R397	0x018d00
R398	0x018e00
R399	0x018f00
R400	0x019000
R401	0x019100
R402	0x019200
R403	0x019300
R404	0x019402
R405	0x019500
R406	0x019600
R407	0x019700
R408	0x01988c
R409	0x019950
R410	0x019a02
R411	0x019b03
R412	0x019c37
R413	0x019d00
R414	0x019e00
R415	0x019f0d
R416	0x01a00f
R417	0x01a102
R418	0x01a208
R419	0x01a30b
R420	0x01a409
R421	0x01a508
R422	0x01a608
R423	0x01a701
R424	0x01a875
R425	0x01a900
R426	0x01aa00
R427	0x01ab10
R428	0x01ac0d
R429	0x01ad01
R430	0x01ae07
R431	0x01af00
R432	0x01b000
R433	0x01b100
R434	0x01b20d
R435	0x01b355
R436	0x01b455
R437	0x01b555
R438	0x01b655
R439	0x01b755
R440	0x01b824
R594	0x025200
R595	0x025300
R596	0x025400
R597	0x025500
R598	0x025600
R599	0x025700
R600	0x025800
R601	0x025900
R602	0x025a2c
R603	0x025bc4
R604	0x025c55
R605	0x025d4c
R606	0x025e49
R607	0x025f49
R608	0x026082
R609	0x02612d
R626	0x027200
R627	0x027300
R628	0x027400
R629	0x027500
R630	0x027600
R631	0x027705
R632	0x027801
R633	0x027900
R634	0x027a00
R635	0x027b00
R636	0x027c01

# APLL1/DPLL1 mux Registers


# output channel 1 Registers
R58	0x003a18
R59	0x003b00
R60	0x003c00
R61	0x003d01
R30	0x001e00	 &	 0x000000c
R51	0x00333e	 &	 0x0000002
R83	0x005300	 &	 0x0000002
R85	0x005512	 &	 0x0000038
R88	0x00583f	 &	 0x0000002

# output channel 2 and 3 Registers
R64	0x004000
R65	0x004100
R66	0x004201
R51	0x00333e	 &	 0x0000004
R83	0x005300	 &	 0x0000004
R86	0x005612	 &	 0x0000007
R88	0x00583f	 &	 0x0000004

# output channel 2 only Registers
R62	0x003e18
R30	0x001e00	 &	 0x0000030

# output channel 3 only Registers
R63	0x003f18
R30	0x001e00	 &	 0x00000c0

# output channel 4 and 5 Registers
R69	0x004500
R70	0x004600
R71	0x004778
R51	0x00333e	 &	 0x0000008
R83	0x005300	 &	 0x0000008
R86	0x005612	 &	 0x0000038
R88	0x00583f	 &	 0x0000008

# output channel 4 only Registers
R67	0x004318
R31	0x001f00	 &	 0x0000003

# output channel 5 only Registers
R68	0x004418
R31	0x001f00	 &	 0x000000c

# output channel 6 Registers
R72	0x004818
R73	0x004900
R74	0x004a00
R75	0x004b78
R31	0x001f00	 &	 0x0000030
R51	0x00333e	 &	 0x0000010
R83	0x005300	 &	 0x0000010
R87	0x005712	 &	 0x0000007
R88	0x00583f	 &	 0x0000010

# output channel 7 Registers
R76	0x004c18
R77	0x004d00
R78	0x004e00
R79	0x004f00
R80	0x005000
R81	0x005178
R31	0x001f00	 &	 0x00000c0
R51	0x00333e	 &	 0x0000020
R83	0x005300	 &	 0x0000020
R87	0x005712	 &	 0x0000038
R88	0x00583f	 &	 0x0000020

# Other APLL1/DPLL1 Registers
R17	0x001100				 # LOPL_DPLL1_MASK, LOFL_DPLL1_MASK, HIST1_MASK, HLDOVR1_MASK, REFSWITCH1_MASK, LOR_MISSCLK1_MASK, LOR_FREQ1_MASK, LOR_AMP1_MASK
R20	0x001400				 # LOPL_DPLL1_POL, LOFL_DPLL1_POL, HIST1_POL, HLDOVR1_POL, REFSWITCH1_POL, LOR_MISSCLK1_POL, LOR_FREQ1_POL, LOR_AMP1_POL
R583	0x024700				 # DPLL1_FDEV[31:24]
R584	0x024800				 # DPLL1_FDEV[23:16]
R585	0x024900				 # DPLL1_FDEV[15:8]
R586	0x024a00				 # DPLL1_FDEV
R16	0x001000	 &	 0x0000004		 # LOL_PLL1_MASK
R19	0x001300	 &	 0x0000004		 # LOL_PLL1_POL
R50	0x003200	 &	 0x0000003		 # GPIO6_FDEV_EN, GPIO5_FDEV_EN
R82	0x00525a	 &	 0x000000f		 # PLL1_SEC_CH47_SYNC_BNK, PLL1_SEC_CH03_SYNC_BNK, PLL1_PRI_CH47_SYNC_BNK, PLL1_PRI_CH03_SYNC_BNK
R176	0x00b009	 &	 0x000000a		 # REF_A_DPLL1_EN, REF_B_DPLL1_EN
R182	0x00b633	 &	 0x000000f		 # MUTE_DPLL1_TCXO, MUTE_DPLL1_PHLOCK, MUTE_DPLL1_LOCK, MUTE_APLL1_LOCK
R580	0x024402	 &	 0x0000007		 # DPLL1_DCO_SEL_REF_TCXOB, DPLL1_IGNORE_GPIO_PIN, DPLL1_FDEV_EN
R582	0x024600	 &	 0x000003f		 # DPLL1_FDEV[37:32]

# General Registers
R40	0x0028ce				 # RESERVED
R42	0x002abf				 # RESERVED
R170	0x00aa00				 # MEMDAR
R172	0x00acfe				 # RAMDAT
R174	0x00ae00				 # NVMUNLK
R184	0x00b8f0				 # GPIO_OUT, GPIO6_STAT_POL, GPIO5_STAT_POL, STAT1_POL, STAT0_POL
R12	0x000c3b	 &	 0x00000fb		 # RESET_SW, SYNC_SW, SYNC_AUTO_APLL, SYNC_MUTE, PLLSTRTMODE, AUTOSTRT
R16	0x001000	 &	 0x0000033		 # LOS_FDET_TCXO_MASK, LOS_FDET_XO_MASK, LOS_TCXO_MASK, LOS_XO_MASK
R19	0x001300	 &	 0x0000033		 # LOS_FDET_TCXO_POL, LOS_FDET_XO_POL, LOS_TCXO_POL, LOS_XO_POL
R25	0x001900	 &	 0x0000003		 # INT_AND_OR, INT_EN
R32	0x002000	 &	 0x0000003		 # RESERVED
R33	0x002105	 &	 0x000000f		 # RESERVED
R34	0x002205	 &	 0x000000f		 # RESERVED, LVL_SEL_XO_DIFF
R36	0x002403	 &	 0x000000f		 # XO_FDET_BYP, XO_DETECT_BYP, XO_BUFSEL
R38	0x002610	 &	 0x000000f		 # RESERVED
R46	0x002e40	 &	 0x000007f		 # STAT0_SEL
R47	0x002f41	 &	 0x000007f		 # STAT1_SEL
R48	0x00304a	 &	 0x000007f		 # GPIO5_STAT_SEL
R49	0x003150	 &	 0x000007f		 # GPIO6_STAT_SEL
R84	0x005401	 &	 0x000003f		 # O_CH4_7_ZERODLY_EN, O_CH0_3_ZERODLY_EN
R89	0x005900	 &	 0x0000003		 # REF_BYPASS_MUX
R164	0x00a424	 &	 0x000003f		 # REF_1P2V_LDO_TRIM, LDO_TRIM
R167	0x00a700	 &	 0x0000010		 # RESERVED
R169	0x00a900	 &	 0x000001f		 # MEMADR[12:8]
R175	0x00af00	 &	 0x000000f		 # REGCOMMIT_PG
R185	0x00b900	 &	 0x000009f		 # DPLL_TCXO_MDIV_DBLR, DPLL_TCXO_MDIV
R186	0x00ba11	 &	 0x0000037		 # TCXO_DETECT_MODE, TCXO_FDET_BYP, TCXO_DETECT_BYP, TCXO_BUFSEL
R187	0x00bb95	 &	 0x000000f		 # LVL_SEL_REF1, LVL_SEL_REF0
R188	0x00bc15	 &	 0x000000f		 # LVL_SEL_REF3, LVL_SEL_REF2
R205	0x00cd02	 &	 0x00000f0		 # RESERVED
R218	0x00da00	 &	 0x0000001		 # SET_HOLD_CLK
R678	0x02a640	 &	 0x00000e0		 # RESERVED
R736	0x02e000	 &	 0x0000018		 # OCXO_MDIV_STATUS_OUT_SEL

# APLL1/DPLL1 Reset
R677	0x02a501	 &	 0x000001
R677	0x02a500	 &	 0x000001

# Last power up the outputs
R51	0x00333e	 &	 0x00003e
    DPLL2_v025.txt 
    # First power down the outputs changing
R51	0x00333f	 &	 0x000001

# APLL2/DPLL2 Registers
R96	0x006002
R97	0x006103
R98	0x006244
R99	0x00630f
R100	0x006417
R101	0x006505
R129	0x008100
R130	0x008239
R131	0x00834a
R132	0x0084aa
R133	0x0085aa
R134	0x0086aa
R135	0x0087ab
R136	0x008803
R137	0x008900
R138	0x008a01
R139	0x008b00
R140	0x008c00
R141	0x008d00
R142	0x008e00
R143	0x008f00
R144	0x009000
R145	0x00914a
R146	0x0092bc
R147	0x0093ae
R148	0x0094a9
R149	0x009580
R150	0x009600
R151	0x009702
R152	0x009800
R153	0x009901
R154	0x009a01
R155	0x009b77
R161	0x00a100
R162	0x00a20d
R163	0x00a329
R300	0x012c00
R301	0x012d03
R441	0x01b92f
R442	0x01ba0a
R443	0x01bb00
R444	0x01bc00
R445	0x01bd00
R446	0x01be01
R447	0x01bf00
R448	0x01c000
R449	0x01c100
R450	0x01c200
R451	0x01c300
R452	0x01c400
R453	0x01c500
R454	0x01c600
R455	0x01c700
R456	0x01c800
R457	0x01c906
R458	0x01ca8b
R459	0x01cb00
R460	0x01cc00
R461	0x01cd00
R462	0x01ce00
R463	0x01cf00
R464	0x01d0b0
R465	0x01d107
R466	0x01d200
R467	0x01d302
R468	0x01d4a9
R469	0x01d500
R470	0x01d600
R471	0x01d700
R472	0x01d81d
R473	0x01d91f
R474	0x01da1d
R475	0x01db00
R476	0x01dc00
R477	0x01dd00
R478	0x01de00
R479	0x01df00
R480	0x01e000
R481	0x01e100
R482	0x01e200
R483	0x01e300
R484	0x01e4a1
R485	0x01e500
R486	0x01e6a0
R487	0x01e700
R488	0x01e820
R489	0x01e909
R490	0x01ea01
R491	0x01eb00
R492	0x01ec2c
R493	0x01ed06
R494	0x01ee02
R495	0x01ef06
R496	0x01f001
R497	0x01f100
R498	0x01f20d
R499	0x01f317
R500	0x01f402
R501	0x01f50f
R502	0x01f603
R503	0x01f7db
R504	0x01f855
R505	0x01f95a
R506	0x01fa5a
R507	0x01fb5a
R508	0x01fc5a
R509	0x01fd5a
R510	0x01fe5a
R511	0x01ffff
R512	0x0200ff
R513	0x0201ff
R514	0x0202ff
R515	0x0203ff
R516	0x020424
R517	0x020500
R518	0x02060a
R519	0x020700
R520	0x020800
R521	0x020900
R522	0x020a01
R523	0x020b06
R524	0x020cd4
R525	0x020d67
R526	0x020e25
R527	0x020f00
R528	0x021014
R529	0x021100
R530	0x021200
R531	0x021300
R532	0x021401
R533	0x021506
R534	0x0216d4
R535	0x021767
R536	0x021825
R537	0x021900
R538	0x021a00
R539	0x021b00
R540	0x021c00
R541	0x021d00
R542	0x021e00
R543	0x021f02
R544	0x022000
R545	0x022104
R546	0x02224c
R547	0x02238f
R548	0x022450
R549	0x022501
R550	0x022602
R551	0x02276f
R552	0x022800
R553	0x022900
R554	0x022a0c
R555	0x022b0d
R556	0x022c04
R557	0x022d08
R558	0x022e0d
R559	0x022f0c
R560	0x023008
R561	0x023108
R562	0x023200
R563	0x023378
R564	0x023400
R565	0x023500
R566	0x023612
R567	0x023710
R568	0x023801
R569	0x023901
R570	0x023a00
R571	0x023b00
R572	0x023c00
R573	0x023d24
R574	0x023eaa
R575	0x023faa
R576	0x0240aa
R577	0x0241aa
R578	0x0242ab
R579	0x024324
R610	0x026245
R611	0x026345
R612	0x026440
R613	0x026500
R614	0x026600
R615	0x026700
R616	0x02686e
R617	0x026900
R618	0x026ac0
R619	0x026b44
R620	0x026c16
R621	0x026d0e
R622	0x026e83
R623	0x026f10
R624	0x02700c
R625	0x027109
R637	0x027d00
R638	0x027e00
R639	0x027f00
R640	0x028000
R641	0x028100
R642	0x028205
R643	0x028301
R644	0x028400
R645	0x028500
R646	0x028600
R647	0x028701

# Input0 Registers
R193	0x00c100
R194	0x00c200
R195	0x00c342
R206	0x00ce00
R207	0x00cf00
R208	0x00d03c
R219	0x00db00
R220	0x00dc6e
R221	0x00dd00
R222	0x00de78
R236	0x00ec00
R237	0x00ed06
R238	0x00ee5b
R239	0x00ef72
R240	0x00f000
R241	0x00f11e
R242	0x00f284
R243	0x00f385
R268	0x010c0e
R272	0x011000
R273	0x011198
R274	0x011296
R275	0x011380
R288	0x01203f

# More Input Registers.  Inputs = [0]
R43	0x002b0f	 &	 0x0000001
R44	0x002c88	 &	 0x000000f
R183	0x00b755	 &	 0x0000003
R189	0x00bd19	 &	 0x000003f
R205	0x00cd02	 &	 0x0000001
R235	0x00eb00	 &	 0x0000003
R292	0x012400	 &	 0x0000007
R297	0x012901	 &	 0x0000007

# APLL2/DPLL2 mux Registers


# output channel 0 Registers
R52	0x00343e
R53	0x003502
R54	0x003600
R55	0x003700
R56	0x003800
R57	0x00396e
R30	0x001e00	 &	 0x0000003
R51	0x00333e	 &	 0x0000001
R83	0x005300	 &	 0x0000001
R85	0x005512	 &	 0x0000007
R88	0x00583f	 &	 0x0000001

# Other APLL2/DPLL2 Registers
R18	0x001200				 # LOPL_DPLL2_MASK, LOFL_DPLL2_MASK, HIST2_MASK, HLDOVR2_MASK, REFSWITCH2_MASK, LOR_MISSCLK2_MASK, LOR_FREQ2_MASK, LOR_AMP2_MASK
R21	0x001500				 # LOPL_DPLL2_POL, LOFL_DPLL2_POL, HIST2_POL, HLDOVR2_POL, REFSWITCH2_POL, LOR_MISSCLK2_POL, LOR_FREQ2_POL, LOR_AMP2_POL
R589	0x024d00				 # DPLL2_FDEV[31:24]
R590	0x024e00				 # DPLL2_FDEV[23:16]
R591	0x024f00				 # DPLL2_FDEV[15:8]
R592	0x02500a				 # DPLL2_FDEV
R16	0x001000	 &	 0x0000008		 # LOL_PLL2_MASK
R19	0x001300	 &	 0x0000008		 # LOL_PLL2_POL
R50	0x003200	 &	 0x00000c0		 # GPIO4_FDEV_EN, GPIO3_FDEV_EN
R19	0x001300	 &	 0x00000f0		 # PLL2_SEC_CH47_SYNC_BNK, PLL2_SEC_CH03_SYNC_BNK, PLL2_PRI_CH47_SYNC_BNK, PLL2_PRI_CH03_SYNC_BNK
R176	0x00b009	 &	 0x0000005		 # REF_A_DPLL2_EN, REF_B_DPLL2_EN
R182	0x00b633	 &	 0x00000f0		 # MUTE_DPLL2_TCXO, MUTE_DPLL2_PHLOCK, MUTE_DPLL2_LOCK, MUTE_APLL2_LOCK
R581	0x024500	 &	 0x0000007		 # DPLL2_DCO_SEL_REF_TCXOB, DPLL2_IGNORE_GPIO_PIN, DPLL2_FDEV_EN
R588	0x024c00	 &	 0x000003f		 # DPLL2_FDEV[37:32]

# General Registers
R40	0x0028ce				 # RESERVED
R42	0x002abf				 # RESERVED
R170	0x00aa00				 # MEMDAR
R172	0x00acfe				 # RAMDAT
R174	0x00ae00				 # NVMUNLK
R184	0x00b8f0				 # GPIO_OUT, GPIO6_STAT_POL, GPIO5_STAT_POL, STAT1_POL, STAT0_POL
R12	0x000c3b	 &	 0x00000fb		 # RESET_SW, SYNC_SW, SYNC_AUTO_APLL, SYNC_MUTE, PLLSTRTMODE, AUTOSTRT
R16	0x001000	 &	 0x0000033		 # LOS_FDET_TCXO_MASK, LOS_FDET_XO_MASK, LOS_TCXO_MASK, LOS_XO_MASK
R19	0x001300	 &	 0x0000033		 # LOS_FDET_TCXO_POL, LOS_FDET_XO_POL, LOS_TCXO_POL, LOS_XO_POL
R25	0x001900	 &	 0x0000003		 # INT_AND_OR, INT_EN
R32	0x002000	 &	 0x0000003		 # RESERVED
R33	0x002105	 &	 0x000000f		 # RESERVED
R34	0x002205	 &	 0x000000f		 # RESERVED, LVL_SEL_XO_DIFF
R36	0x002403	 &	 0x000000f		 # XO_FDET_BYP, XO_DETECT_BYP, XO_BUFSEL
R38	0x002610	 &	 0x000000f		 # RESERVED
R46	0x002e40	 &	 0x000007f		 # STAT0_SEL
R47	0x002f41	 &	 0x000007f		 # STAT1_SEL
R48	0x00304a	 &	 0x000007f		 # GPIO5_STAT_SEL
R49	0x003150	 &	 0x000007f		 # GPIO6_STAT_SEL
R84	0x005401	 &	 0x000003f		 # O_CH4_7_ZERODLY_EN, O_CH0_3_ZERODLY_EN
R89	0x005900	 &	 0x0000003		 # REF_BYPASS_MUX
R164	0x00a424	 &	 0x000003f		 # REF_1P2V_LDO_TRIM, LDO_TRIM
R167	0x00a700	 &	 0x0000010		 # RESERVED
R169	0x00a900	 &	 0x000001f		 # MEMADR[12:8]
R175	0x00af00	 &	 0x000000f		 # REGCOMMIT_PG
R185	0x00b900	 &	 0x000009f		 # DPLL_TCXO_MDIV_DBLR, DPLL_TCXO_MDIV
R186	0x00ba11	 &	 0x0000037		 # TCXO_DETECT_MODE, TCXO_FDET_BYP, TCXO_DETECT_BYP, TCXO_BUFSEL
R187	0x00bb95	 &	 0x000000f		 # LVL_SEL_REF1, LVL_SEL_REF0
R188	0x00bc15	 &	 0x000000f		 # LVL_SEL_REF3, LVL_SEL_REF2
R205	0x00cd02	 &	 0x00000f0		 # RESERVED
R218	0x00da00	 &	 0x0000001		 # SET_HOLD_CLK
R678	0x02a640	 &	 0x00000e0		 # RESERVED
R736	0x02e000	 &	 0x0000018		 # OCXO_MDIV_STATUS_OUT_SEL

# APLL2/DPLL2 Reset
R677	0x02a502	 &	 0x000002
R677	0x02a500	 &	 0x000002

# Last power up the outputs
R51	0x00333e	 &	 0x000001
    5661.HexRegisterValues.txt 
    R0	0x000010
R1	0x00010B
R2	0x000235
R3	0x000301
R4	0x0004FB
R5	0x0005FF
R6	0x0006FA
R7	0x0007FF
R8	0x000802
R9	0x000900
R10	0x000AC0
R11	0x000B08
R12	0x000C3B
R13	0x000D00
R14	0x000EC0
R15	0x000F00
R16	0x001000
R17	0x001100
R18	0x001200
R19	0x001300
R20	0x001400
R21	0x001500
R22	0x001600
R23	0x001700
R24	0x001800
R25	0x001900
R26	0x001A0F
R27	0x001B55
R28	0x001C55
R29	0x001D00
R30	0x001E00
R31	0x001F00
R32	0x002000
R33	0x002105
R34	0x002205
R35	0x002334
R36	0x002403
R37	0x002500
R38	0x002610
R39	0x002702
R40	0x0028CE
R41	0x002900
R42	0x002ABF
R43	0x002B0F
R44	0x002C88
R45	0x002D88
R46	0x002E40
R47	0x002F41
R48	0x00304A
R49	0x003150
R50	0x003200
R51	0x00333E
R52	0x00343E
R53	0x003502
R54	0x003600
R55	0x003700
R56	0x003800
R57	0x00396E
R58	0x003A18
R59	0x003B00
R60	0x003C00
R61	0x003D01
R62	0x003E18
R63	0x003F18
R64	0x004000
R65	0x004100
R66	0x004201
R67	0x004318
R68	0x004418
R69	0x004500
R70	0x004600
R71	0x004778
R72	0x004818
R73	0x004900
R74	0x004A00
R75	0x004B78
R76	0x004C18
R77	0x004D00
R78	0x004E00
R79	0x004F00
R80	0x005000
R81	0x005178
R82	0x00525A
R83	0x005300
R84	0x005401
R85	0x005512
R86	0x005612
R87	0x005712
R88	0x00583F
R89	0x005900
R90	0x005A03
R91	0x005B03
R92	0x005C33
R93	0x005D0F
R94	0x005E17
R95	0x005F05
R96	0x006002
R97	0x006103
R98	0x006244
R99	0x00630F
R100	0x006417
R101	0x006505
R102	0x006600
R103	0x006732
R104	0x006800
R105	0x006900
R106	0x006A00
R107	0x006B00
R108	0x006C00
R109	0x006D03
R110	0x006E00
R111	0x006F01
R112	0x007000
R113	0x007100
R114	0x007200
R115	0x007300
R116	0x007400
R117	0x007500
R118	0x0076FF
R119	0x0077FF
R120	0x0078FF
R121	0x0079FF
R122	0x007AFF
R123	0x007B02
R124	0x007C02
R125	0x007D00
R126	0x007E01
R127	0x007F01
R128	0x008077
R129	0x008100
R130	0x008239
R131	0x00834A
R132	0x0084AA
R133	0x0085AA
R134	0x0086AA
R135	0x0087AB
R136	0x008803
R137	0x008900
R138	0x008A01
R139	0x008B00
R140	0x008C00
R141	0x008D00
R142	0x008E00
R143	0x008F00
R144	0x009000
R145	0x00914A
R146	0x0092BC
R147	0x0093AE
R148	0x0094A9
R149	0x009580
R150	0x009600
R151	0x009702
R152	0x009800
R153	0x009901
R154	0x009A01
R155	0x009B77
R156	0x009C00
R157	0x009D00
R158	0x009E03
R159	0x009F0D
R160	0x00A029
R161	0x00A100
R162	0x00A20D
R163	0x00A329
R164	0x00A424
R165	0x00A584
R166	0x00A6FF
R167	0x00A700
R168	0x00A800
R169	0x00A900
R170	0x00AA00
R171	0x00ABFF
R172	0x00ACFE
R173	0x00AD00
R174	0x00AE00
R175	0x00AF00
R176	0x00B009
R177	0x00B1A3
R178	0x00B292
R179	0x00B3DB
R180	0x00B4EA
R181	0x00B529
R182	0x00B633
R183	0x00B755
R184	0x00B8F0
R185	0x00B900
R186	0x00BA11
R187	0x00BB95
R188	0x00BC15
R189	0x00BD19
R190	0x00BE01
R191	0x00BF01
R192	0x00C001
R193	0x00C100
R194	0x00C200
R195	0x00C342
R196	0x00C400
R197	0x00C500
R198	0x00C6D2
R199	0x00C700
R200	0x00C800
R201	0x00C942
R202	0x00CA00
R203	0x00CB00
R204	0x00CC42
R205	0x00CD02
R206	0x00CE00
R207	0x00CF00
R208	0x00D03C
R209	0x00D100
R210	0x00D200
R211	0x00D342
R212	0x00D400
R213	0x00D500
R214	0x00D63C
R215	0x00D700
R216	0x00D800
R217	0x00D93C
R218	0x00DA00
R219	0x00DB00
R220	0x00DC6E
R221	0x00DD00
R222	0x00DE78
R223	0x00DF00
R224	0x00E06E
R225	0x00E100
R226	0x00E278
R227	0x00E300
R228	0x00E46E
R229	0x00E500
R230	0x00E678
R231	0x00E700
R232	0x00E86E
R233	0x00E900
R234	0x00EA78
R235	0x00EB00
R236	0x00EC00
R237	0x00ED06
R238	0x00EE5B
R239	0x00EF72
R240	0x00F000
R241	0x00F11E
R242	0x00F284
R243	0x00F385
R244	0x00F400
R245	0x00F51E
R246	0x00F684
R247	0x00F780
R248	0x00F800
R249	0x00F91E
R250	0x00FA84
R251	0x00FB80
R252	0x00FC00
R253	0x00FD06
R254	0x00FE5B
R255	0x00FF72
R256	0x010000
R257	0x01011E
R258	0x010284
R259	0x010385
R260	0x010400
R261	0x010506
R262	0x01065B
R263	0x010772
R264	0x010800
R265	0x01091E
R266	0x010A84
R267	0x010B85
R268	0x010C0E
R269	0x010D0A
R270	0x010E0A
R271	0x010F0A
R272	0x011000
R273	0x011198
R274	0x011296
R275	0x011380
R276	0x011400
R277	0x011598
R278	0x011696
R279	0x011780
R280	0x011800
R281	0x011998
R282	0x011A96
R283	0x011B80
R284	0x011C00
R285	0x011D98
R286	0x011E96
R287	0x011F80
R288	0x01203F
R289	0x012100
R290	0x012200
R291	0x012300
R292	0x012400
R293	0x012580
R294	0x012600
R295	0x012700
R296	0x012803
R297	0x012901
R298	0x012A80
R299	0x012B00
R300	0x012C00
R301	0x012D03
R302	0x012E2F
R303	0x012F0A
R304	0x013000
R305	0x013100
R306	0x013200
R307	0x013301
R308	0x013400
R309	0x013500
R310	0x013600
R311	0x013700
R312	0x013800
R313	0x013900
R314	0x013A00
R315	0x013B00
R316	0x013C00
R317	0x013D00
R318	0x013E06
R319	0x013F8B
R320	0x014000
R321	0x014100
R322	0x014200
R323	0x014361
R324	0x0144A8
R325	0x0145A0
R326	0x014604
R327	0x014700
R328	0x014803
R329	0x014984
R330	0x014A00
R331	0x014B00
R332	0x014C00
R333	0x014D1C
R334	0x014E00
R335	0x014F00
R336	0x015002
R337	0x015100
R338	0x015200
R339	0x015301
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x0159E0
R346	0x015A00
R347	0x015BA1
R348	0x015C03
R349	0x015D01
R350	0x015E09
R351	0x015F01
R352	0x016000
R353	0x01612C
R354	0x01620F
R355	0x016302
R356	0x016406
R357	0x016501
R358	0x016600
R359	0x01670E
R360	0x016818
R361	0x016902
R362	0x016A0F
R363	0x016B04
R364	0x016C35
R365	0x016D17
R366	0x016E4B
R367	0x016F4B
R368	0x01704B
R369	0x01714B
R370	0x01724B
R371	0x01734B
R372	0x0174FF
R373	0x0175FF
R374	0x0176FF
R375	0x0177FF
R376	0x0178FF
R377	0x017924
R378	0x017A00
R379	0x017B64
R380	0x017C00
R381	0x017D00
R382	0x017E00
R383	0x017F01
R384	0x018005
R385	0x0181F5
R386	0x0182E1
R387	0x018300
R388	0x018400
R389	0x01856E
R390	0x018600
R391	0x018700
R392	0x018800
R393	0x018901
R394	0x018A05
R395	0x018BF5
R396	0x018CE1
R397	0x018D00
R398	0x018E00
R399	0x018F00
R400	0x019000
R401	0x019100
R402	0x019200
R403	0x019300
R404	0x019402
R405	0x019500
R406	0x019600
R407	0x019700
R408	0x01988C
R409	0x019950
R410	0x019A02
R411	0x019B03
R412	0x019C37
R413	0x019D00
R414	0x019E00
R415	0x019F0D
R416	0x01A00F
R417	0x01A102
R418	0x01A208
R419	0x01A30B
R420	0x01A409
R421	0x01A508
R422	0x01A608
R423	0x01A701
R424	0x01A875
R425	0x01A900
R426	0x01AA00
R427	0x01AB10
R428	0x01AC0D
R429	0x01AD01
R430	0x01AE07
R431	0x01AF00
R432	0x01B000
R433	0x01B100
R434	0x01B20D
R435	0x01B355
R436	0x01B455
R437	0x01B555
R438	0x01B655
R439	0x01B755
R440	0x01B824
R441	0x01B92F
R442	0x01BA0A
R443	0x01BB00
R444	0x01BC00
R445	0x01BD00
R446	0x01BE01
R447	0x01BF00
R448	0x01C000
R449	0x01C100
R450	0x01C200
R451	0x01C300
R452	0x01C400
R453	0x01C500
R454	0x01C600
R455	0x01C700
R456	0x01C800
R457	0x01C906
R458	0x01CA8B
R459	0x01CB00
R460	0x01CC00
R461	0x01CD00
R462	0x01CE00
R463	0x01CF00
R464	0x01D0B0
R465	0x01D10F
R466	0x01D200
R467	0x01D302
R468	0x01D4A9
R469	0x01D500
R470	0x01D600
R471	0x01D700
R472	0x01D81D
R473	0x01D91F
R474	0x01DA1D
R475	0x01DB00
R476	0x01DC00
R477	0x01DD00
R478	0x01DE00
R479	0x01DF00
R480	0x01E000
R481	0x01E100
R482	0x01E200
R483	0x01E300
R484	0x01E4A1
R485	0x01E500
R486	0x01E6A0
R487	0x01E700
R488	0x01E820
R489	0x01E909
R490	0x01EA01
R491	0x01EB00
R492	0x01EC2C
R493	0x01ED06
R494	0x01EE02
R495	0x01EF06
R496	0x01F001
R497	0x01F100
R498	0x01F20D
R499	0x01F317
R500	0x01F402
R501	0x01F50F
R502	0x01F603
R503	0x01F7DB
R504	0x01F855
R505	0x01F95A
R506	0x01FA5A
R507	0x01FB5A
R508	0x01FC5A
R509	0x01FD5A
R510	0x01FE5A
R511	0x01FFFF
R512	0x0200FF
R513	0x0201FF
R514	0x0202FF
R515	0x0203FF
R516	0x020424
R517	0x020500
R518	0x02060A
R519	0x020700
R520	0x020800
R521	0x020900
R522	0x020A01
R523	0x020B06
R524	0x020CD4
R525	0x020D67
R526	0x020E25
R527	0x020F00
R528	0x021014
R529	0x021100
R530	0x021200
R531	0x021300
R532	0x021401
R533	0x021506
R534	0x0216D4
R535	0x021767
R536	0x021825
R537	0x021900
R538	0x021A00
R539	0x021B00
R540	0x021C00
R541	0x021D00
R542	0x021E00
R543	0x021F02
R544	0x022000
R545	0x022104
R546	0x02224C
R547	0x02238F
R548	0x022450
R549	0x022501
R550	0x022602
R551	0x02276F
R552	0x022800
R553	0x022900
R554	0x022A0C
R555	0x022B0D
R556	0x022C04
R557	0x022D08
R558	0x022E0D
R559	0x022F0C
R560	0x023008
R561	0x023108
R562	0x023200
R563	0x023378
R564	0x023400
R565	0x023500
R566	0x023612
R567	0x023710
R568	0x023801
R569	0x023901
R570	0x023A00
R571	0x023B00
R572	0x023C00
R573	0x023D24
R574	0x023EAA
R575	0x023FAA
R576	0x0240AA
R577	0x0241AA
R578	0x0242AB
R579	0x024324
R580	0x024402
R581	0x024500
R582	0x024600
R583	0x024700
R584	0x024800
R585	0x024900
R586	0x024A00
R587	0x024B00
R588	0x024C00
R589	0x024D00
R590	0x024E00
R591	0x024F00
R592	0x02500A
R593	0x025101
R594	0x025200
R595	0x025300
R596	0x025400
R597	0x025500
R598	0x025600
R599	0x025700
R600	0x025800
R601	0x025900
R602	0x025A2C
R603	0x025BC4
R604	0x025C55
R605	0x025D4C
R606	0x025E49
R607	0x025F49
R608	0x026082
R609	0x02612D
R610	0x026245
R611	0x026345
R612	0x026440
R613	0x026500
R614	0x026600
R615	0x026700
R616	0x02686E
R617	0x026900
R618	0x026AC0
R619	0x026B44
R620	0x026C16
R621	0x026D0E
R622	0x026E83
R623	0x026F10
R624	0x02700C
R625	0x027109
R626	0x027200
R627	0x027300
R628	0x027400
R629	0x027500
R630	0x027600
R631	0x027705
R632	0x027801
R633	0x027900
R634	0x027A00
R635	0x027B00
R636	0x027C01
R637	0x027D00
R638	0x027E00
R639	0x027F00
R640	0x028000
R641	0x028100
R642	0x028205
R643	0x028301
R644	0x028400
R645	0x028500
R646	0x028600
R647	0x028701
R676	0x02A400
R677	0x02A500
R678	0x02A640
R681	0x02A944
R682	0x02AA44
R683	0x02AB44
R684	0x02AC44
R685	0x02AD44
R686	0x02AE44
R687	0x02AF04
R688	0x02B044
R691	0x02B300
R715	0x02CB00
R716	0x02CC04
R717	0x02CD04
R718	0x02CE04
R719	0x02CF04
R736	0x02E000
R741	0x02E500
R742	0x02E630
R764	0x02FC00
R766	0x02FE00
R767	0x02FF01
R770	0x030200
R771	0x030302
R775	0x030700
R776	0x030801
R784	0x031000
R785	0x031101
    readback.txt 
    R0	0x000010
R1	0x00010B
R2	0x000235
R3	0x000302
R4	0x000400
R5	0x000500
R6	0x0006C4
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  • 0 in reply to michele pedroni
    TI__Expert 6140 points

    Hi Michele, 

    Since you're seeing a frequency error and mentioned this is irrelevant of the reference input, it suggests even when reference input is available DPLL is not locked. I asked for status readback to understand whether reference was validated and selected. And then to see if DPLL is indeed not locked. 

    Looking at the readback.txt file that you have sent, that's is what it shows, reference is not valid DPLL is in holdover mode. Was this during the time reference was connected to the device? 

    Secondly, the configuration was tested on evm and showed no problem, correct? It's now an issue on the actual cpu board. 

    Thanks and regards, Amin

  • 0 in reply to Amin Eshraghi
    Prodigy 180 points

    Hi Amin,

    I confirm that the readback was made with the reference 1PPS connected, and we get the same result even if the reference is not connected. At the moment, we did not test this configuration on the EVM because we do not have it, but we will buy asap to verify the situation.

    I'll be back to you after the tests on EVM.

    Best Regards,

    Michele

  • 0 in reply to michele pedroni
    Prodigy 180 points

    Furthermore, I attach you the CPU board schematic.

    Best Regards,

    Michele

    1803.lmk.pdf

  • 0 in reply to michele pedroni
    TI__Expert 6140 points

    Hi Michele, 

    Testing out on EVM should give us a lot more information. 

    I noticed the status 0 and status 1 signals were set to DPLL1 rdiv and ndiv, the GPIO statuses are also monitoring DPLL1. Your configuration is only using DPLL2 / APLL2 with DPLL1 / APLL1 powered down. It would be more beneficial to monitor DPLL2 signals. 

    Secondly, LOL_PLL2 flag is up, indicating APLL2 is not locked. In this situation I wouldn't expect any reasonable type of output... the 10.000003 MHz you're seeing shows just very small frequency error and does not correlate with a LOL_PLL2 status... so something is off.. 

    Regards, Amin 

  • 0 in reply to Amin Eshraghi
    Prodigy 180 points

    Hello Amir,

    I come back to this issue after having received the Evaluation Kit and loaded the configuration we already discussed.

    The results we get are the same we saw on our custom board, to this seems just a configuration issue. After that, following your advices, we switched STAT0 and STAT1 to DPLL2 Loss of Lock and DPLL2 Holdover Active respectively. Indeed, having a look to "Status & Interrupt" page on TICS Pro, the following interrupts are raised for DPLL2:

    LOPL_DPLL2

    LOFL_DPLL2

    HLDOVR2

    while LOL_PLL2 is NOT set. So, in my undestanding, the APLL2 is locked but there is no phase and frequency lock, so the DPLL2 is in holdover state. Since we have a 1PPS ref, frequency and phase lock are not available anyway, and we have only a jitter threshold control, isn't?

    At this point, could you give me any advice on how to change the configuration to let it work as expected?

    Best Regards,

    Michele

  • 0 in reply to michele pedroni
    TI__Expert 6140 points

    Hi Michele, 

    The APLL can lock just using XO, so that's why it's showing it's locked. You're output frequency error now will be dependent on the XO ppm error. 

    To get the DPLL locked, we first need a valid reference. From the config you sent, looks like you're using IN0.

    - Is their a 1 Hz signal connected to IN0?

    - On the status readback, does it show REF0 valid?

    - Does DPLL2 select REF0? 

    Thanks and regards,

    Amin 

    Note this just a random capture to show visually - obviously if no reference is valid DPLL can't select any of them. 

  • 0 in reply to Amin Eshraghi
    Prodigy 180 points

    Hi Amin,

    we are using the 3-loop configuration and probably the PLL is not only locked to XO but also to TCXO (infact, ignoring the TCXO with a 2-loop configuration leads to a much higher frequency error). That's why the output frequency is so close to the expected value. However, we can say now that the reference is not valid or at least not recognized by the LMK05028: a 1PPS signal is connected to IN0 as it is supposed to be, but REF0VALSTAT is NOT checked and DPLL2_REFSEL_STAT show Holdover state.

    At this point, we should focus on the reference signal. These are 2 oscilloscope screenshots which show the 1PPS reference we have on IN0. Could you check if you see something wrong?

    Best Regards,

    Michele

  • 0 in reply to michele pedroni
    TI__Expert 6140 points

    Hi Michele, 

    Yes, you probably have 2 loops locked, but TCXO is used for TCXO DPLL. So the APLL can get locked just using XO reference. 

    Why is the duty cycle so bad? It looks like the P-duty cycle is only around 20%. 

    Regards,

    Amin 

  • 0 in reply to Amin Eshraghi
    Prodigy 180 points

    HI Amin,

    he have made a step forward in this issue. The duty cycle was around 20% because this is the standard GPS setting for the 1PPS output. After trying different configurations (even with the square ware generator), we realized that a 20% duty cycle is not suitable as a reference input and thus we reconfigured it to 50%, both in GPS and the generator. With this setting, LMK05028 now detect a valid 1PPS reference and DPLL2 looks locked to IN0 REF. Unfortunately, the output frequency looks much unstable, going back and forth from 9.9979MHz to 10.023MHz approximately. If we remove the reference, the system goes to holdover mode and the frequency corrections are stopped to the last value.

    Could you suggest some other setting to change in order to correct this situation? At the moment, DPLL2 is set ZDM mode on OUT0.

    Best regards,

    Michele

  • 0 in reply to michele pedroni
    TI__Expert 6140 points

    Hi Michele, 

    Glad there's been progress made with validating the reference and DPLL locking. 

    The frequency measurement, is it being done on an oscilloscope? Do you have access to a frequency counter or a phase noise analyzer that can be used? And can we sync the reference input (1 pps GPS generator) to the end equipment doing the measurement? 

    I suspect it's either a measurement technique error or DPLL is not locked. Another way to monitor this is to bring out reference ndiv and rdiv on status channel (image of this on my previous posts) and monitor them on a scope. These 2 signals should either be in phase or 180 phase shifted once DPLL locks. On startup/reset/pdn you will see them adjusting and then they should settle into a 0 phase or 180 phase when DPLL locks. If they continue to move around that means DPLL has not locked. 

    Thanks and regards, Amin

  • 0 in reply to Amin Eshraghi
    Prodigy 180 points

    Hi Amin,

    actually we are using not just the oscilloscope but also a frequency counter and we can even synchronize the 1PPS input with the frequency output.

    We brought the NDIV and RDIV on status channels as you suggested and this is the result:

    Indeed, if possible, please provide us a .tcs file with a fully tested configuration to generate an output of whatever frequency from a 1PPS reference. We would like to test it and check if the results are similar.

    Best Regards,

    Michele

  • 0 in reply to michele pedroni
    TI__Expert 6140 points

    Hi Michele, 

    Apologies for the long delay.. 

    The ndiv / rdiv signals look good, I assume they're stable and not even moving. 

    So when DPLL is locked, you see unstable output with frequency moving between 9.9979MHz to 10.023MHz? and this is done with frequency counter that's synced to the reference input, correct? 

    This seems to suggest DPLL is still trying to lock... what are the status signals again? Does is show the ref in that's applied as valid, dpll selects that reference and dpll is frequency and phase locked?  

    Also another note on 1 pps, it does take 2 - 3 minutes the DPLL to lock so please make sure you wait long enough. 

    Does disabling zdm mode, make any change? 

    Lastly I've attached a 1 pps configuration that's been tested perhaps we can look at this one to rule out any system setups. 

    Thanks and regards, Amin

    IN1PPS_LMK05028_0124B_2019.tcs

  • 0 in reply to Amin Eshraghi
    Prodigy 180 points

    Hi Amin,


    we tried the configuration file you sent us and it seems to  work correctly: the 156.25MHz output is generated as expected, both starting with an active 1PPS reference or activating it some minutes after the EVM boot. After that, we modified your TCS file, configuring a 10MHz output on OUT0 from DPLL2 and another 10MHz output on OUT7 from DPLL1. We performed again some tests and we found the following issues:

    - starting with an active 1PPS source, OUT0 looks very precise, but in 1 case out of ten it stabilized with +17Hz offset; OUT7 always had about +986Hz offset

    - starting without an active 1PPS source and activating it some minutes after, we got identical results on OUT7 but in 1 test out of 5 we had a huge offset on OUT0 (+21805Hz)

    I attach you the configuration file, plus a report table with all the tests we made:



    It seems we are not so far from the solution, but we should get rid of that offset we saw at the end of some tests: LMK05028 looks locked, but the frequency is incorrect and we don't know how to correct this situation once it eventually happens. Is there any configuration change we may try?


    Best Regards,


    Michele

  • 0 in reply to michele pedroni
    Prodigy 180 points

    Hi Amin,

    could you additional suggest us how to use the DCO mode to further adjust the output frequency? We tried to use it in several different ways but no effect was seen on OUT0.

    Best Regards,

    Michele

  • 0 in reply to michele pedroni
    TI__Expert 6140 points

    Hi Michele, 

    Did you review datasheet section DCO mode? Because you're using 3 loop mode, the DCO option is with reference DPLL and that's what we're having issues with locking on your configuration. So without locking it, we won't be able to get DCO to work. 

    Furthermore, since we're using a 1 pps input and a really small lbw for the dpll (IIRC is 20 mHz), DCO may not even be an option. 

    I will double check and get back to you. 

    Thanks and regards,

    Amin 

  • 0 in reply to Amin Eshraghi
    Prodigy 100 points

    Dear Amin,

     

    we have been stuck on this issue for a month.

    We have deadlines to meet and a batch of assembled boards to deliver and we are concerned about the performance of the LMK05028.

     

    Summarizing our history:

     

    Our goal is to output 10Mhz frequency phase-locked with 1 pps input.

     

    Our steps:

     

    - we developed and assembled our hardware

    - we asked for your support

    - we purchased the evaluation board

    - we asked for a demo code

    - we asked for a working configuration

     

    None of the aforementioned steps work properly.

     

    The evaluation board doesn’t even work with the .tcs demo code you sent us.

     

    The board correctly locks the frequency 85% of the times.

    In the remaining 15% of the times it appears to be correctly locked from internal registers but the external clock counter (Agilent 53131A) reads a frequency with an offset of some hundreds of hertz.

     

    Please give us the right support to make it work or we will be forced to face a change in architecture and components having so far lost time and money.

     

    Regards,

    Michele

  • 0 in reply to Michele Pedroni
    TI__Expert 6140 points

    Hi Michele, 

    I understand your frustrations and apologies from my end not having been able to resolve the issue. Without having access to lab (due to Covid19) and being able to go in to test things, it's been hard to provide guidance or examine exactly where the problem could be. 

    I am planning to go into lab this week to test this out and provide something that works on the evm. 

    On that note, I'm confused by this note "The evaluation board doesn’t even work with the .tcs demo code you sent us." I thought the .tcs file that I shared you guys were able to load and lock to 1 pps? Did I misunderstand that? 

    The next comment with regards to working 85% of the time and showing issues 15% of the time, is this for various configurations? As far as I know the configuration that you have been working on and trying to lock, the reference DPLL hasn't locked. 

    Thanks and regards,

    Amin 

  • 0 in reply to Amin Eshraghi
    Prodigy 180 points

    Hi Amin,

    unfortunately the LMK05028 shows the same behaviour even if we load you .tcs file. The 85%working-15%not-working statistics refer to a single configuration (yours or modified by us to get the 10MHz output) restarted from boot many times: in the "not working" situation, the chip appears locked from the status register and correctly detects the 1PPS ref, but the output frequency has an offset from the nominal value. The only way to recover from this error is resetting the chip and wait for a new lock again: of course this procedure is frustrating and not acceptable in our application. If we can't find a solution, we will switch to a self made PLL tailored for our needs.

    Best Regards,

    Michele Pedroni

  • 0 in reply to michele pedroni
    TI__Expert 6140 points

    Hi Michele, 

    I went back and reviewed the thread, I think at some point I got confused. 

    The original .tcs file that you shared did not have correct lbw for 1 pps. It should be the ~20 mHz range for 1 pps input. I see in the new image (test_0506) that I was finally able to get access to, this has been corrected. I assume this was generated off of the .tcs file for 1 pps that I shared, with updates being made to 10 MHz output frequency (VCO frequency is updated). 

    I also reviewed the test document, just to confirm, all frequency measurements are take when reference DPLL has locked? This is when LOFL and LOPL flags would clear from reference. And each iteration is through a soft chip reset? So: 

    1 PPS ON: reset, wait for DPLL LOFL and LOPL to clear, measure output frequency

    1 PPS OFF/ON: 1 pps off, reset, 1 pps on, wait for DPLL LOFL and LOPL to clear and measure output frequency?

    Is that the testing that was done? Or was there never any wait for LOPL/LOFL to clear? Or was it a generic wait time and we're perfectly capturing some instances where DPLL has locked and other instances where it still hasn't locked - in which case output frequency error is dependent on the ppm/ppb of the TCXO source. I know you said status shows the same thing - so then this wouldn't be possible. 

    The expected behavior is if 1 pps source is synced to the frequency counter, once reference DPLL locks (LOFL / LOPL) clear, you should be measuring the expected output, 10 MHz. If then you turn 1 pps off, you would go into holdover - which should hold the frequency from before. If DPLL never locked, the frequency error is dependent on the other sources, TCXO if TCXO DPLL locks, XO if only APLL has locked. 

    I was in lab today, but I was only looking at your original image unfortunately as I hadn't been granted access yet to the files that you had shared above. But the next time I'll go in (should be this week) I will look the test_0506 file and see if I can replicate your results that's why I'm trying to perfectly understand how the testing was done. 

    Thanks and regards,

    Amin 

  • 0 in reply to Amin Eshraghi
    Prodigy 180 points

    Hi Amin,

    when we performed those tests, we considered a virtual "timeout" of 10 minutes after the 1PPS ON; this because in our application it is not acceptable to have a longer wait for the initial lock. At the end, the chip always detects a good 1PPS REF (no holdover state) but usually LOPL and LOFL flags are not both cleared; in particular, when the frequency lock looks very close (almost coincident) with the target, LOPL is cleared and LOFL may be cleared or not. Alternatively, when the lock is NOT good, bot flags are set, even if the 1PP REF is good. In this situation, even if we wait for a much longer time, the output frequecy do not have further corrections and keeps an unacceptable offset: the only way to recover is to reset the chip.

    Actually we were misleaded regarding the LOPL/LOFL actual meaning, because the output frequency may lock precise even if those flags are not both cleared. However, we can't understand what's the proper configuration, since the 1PPS REF is good (no holdover state and phase jitter is far below 63us) and we cannot see any other source of errors.

    Best regards,

    Michele Pedroni

  • 0 in reply to michele pedroni
    TI__Expert 6140 points

    Hi Michele, 

    I've made some changes to the .tcs file and tested in lab yesterday. This should have far more reliable times with regards to DPLL lock. 

    The reference validation is the validation timer. the detectors have to pass for that amount of time for the reference to be considered valid (only the 1-pps jitter threshold). In this case the reference validation timer was 0.8s so pretty much by 1s mark you will see ref valid flag and DPLL no longer showing holdover. 

    However DPLL lock time for a 1pps input can be considerably slower. With the updates I've made I was seeing about ~1-2 min for frequency lock, and ~3-4 min for phase lock, so these should perfectly fall within the 10 min requirement. 

    Please test this file and let me know your findings. 

    Thanks and regards,

    Amin 

    test_0506_updated.tcs

  • 0 in reply to Amin Eshraghi
    Prodigy 100 points

    Hello Amin,

    Thanks to your help now the demo board seems to work as expected.

     

    However to adapt the FW chip to our hardware and to save power, we have made the following changes:

     

    • Disabled output 7
    • Disabled input 1

     

    With the aforementioned changes, the flags LOPL2 and LOFL remain set, so the board is not locking.

     

    Can you please check this configuration on your evm ?

     

    Regards,

    Michele

  • 0 in reply to Michele Pedroni
    TI__Expert 6140 points

    Hi Michele, 

    Did you do a runscript in order to make those changes and that's when things didn't work? 

    To disable output 7, all that needs to happen is to change output 7 type to "disabled" and power down the channel. I would also suggest powering down APLL1, that's going to be the big power saver. 

    With regards to input 1, there's no enable/disable. So having runscript with it on, just programs the registers, but if no clock is connected then the internal buffer isn't on and there shouldn't be really any current/power associated with it. 

    Here's updated .tcs in line with steps above: test_0506_updated2_PDN-PLL1nCH7.tcs

    Please note that LOPL and LOFL for DPLL1 will be flagged now, as they're not being used with the PLL1 powerdown. 

    Thanks and regards,

    Amin 

    Out 7 PDN and disable 

    APLL1 PDN - 

  • 0 in reply to Amin Eshraghi
    Prodigy 100 points

    Hello Amin,

     

    Yes we ran the runscript.

    The situation we have with your updated .tcs file on our EVM is the same as we have with our changes.

    The system appears to be very unstable and flags LOPL2 and LOFL2 are not cleared.

     

    A strange thing that happens when we make changes disabling PPL1 and out 7, is that if we try to go back to the previous scenario and do a runscript, the system is not restored to the previous working state and LOPL and LOFL flags continue to be set.

     

    Another problem (in our hardware) is that the system is not trying to adjust the output frequency.

    We downloaded on our hardware the same working configuration on our evm (the one with output 7 and PLL1), using EVM’s I2C lines.

    When it turns on, first it is on holdover then when it gets the PPS, it pulls up to a higher range (something like 10.021.xxx Hz) and hangs there without adjusting it.

    I also tried to connect EVM’s system clocks (Xo and TCXO) with our HW without success.

    Do you have any idea what could it be ?

    I checked our schematic with the EVM and it seems to be correct.

     

    Thanks,

    MIchele6102.lmk.pdf

  • 0 in reply to Michele Pedroni
    TI__Expert 6140 points

    Hi Michele, 

    First note on "A strange thing that happens when we make changes disabling PPL1 and out 7, is that if we try to go back to the previous scenario and do a runscript, the system is not restored to the previous working state and LOPL and LOFL flags continue to be set."

    Performing a runscript recalculates DPLL settings and will reset the lock thresholds for both frequency and phase. It will also set some other registers that will then manually need to be changed, at least from the testing I did in lab. So performing a runscript and not being able to achieve lock is understandable as the software might need some updates for 1 pps configurations. And furthermore, there shouldn't be a need to do a runscript any more if we have a working .tcs file for 1 pps - the updates that we're discussing shouldn't require any calculations that need the runscript and runscript is changing things that we don't want changed. 

    So going back just to confirm: 

    - The configuration with APLL1 and APLL2 as well as DPLL1 and DPLL2 performs as expected and everything locks 

    - Powering down APLL1, and disabling output 7, and loading that .tcs (no runscript ran at any point) DPLL2 cannot lock, is that correct? This is the part that doesn't make any sense as we shouldn't be impacting anything on DPLL2.. 

    What happens if you go through GUI and update rather than load the .tcs file I provided. So start with working config (APLL1 and CH7) active. And step by step go through power down CH7, disable CH7 and finally Powerdown PLL1. At which step, does OUT0 coming from DPLL2 lose frequency and/or status of DPLL2 show holdover. 

    With regards to the working configuration not working on your board. I'm assuming at no point the reference DPLL locked, correct? Was it reading the reference as valid and DPLL just not locking, or was reference never valid? Next was the frequency error, the 10.0021xx MHz any different when you were using your TCXO vs connecting the TCXO from our EVM? Also, if you can perform a register dump and send that file, I can look at it. 

    Thanks and regards, Amin 

  • 0 in reply to Amin Eshraghi
    Prodigy 100 points

    Hi Amin,

     

    Sorry I missed that you manually adjusted some parameters. 

    About the steps:

     >The configuration with APLL1 and APLL2 as well as DPLL1 and DPLL2 performs as expected and everything locks

    That’s correct, it does.

    test_0506_updated_regmap.txt 
    R0	0x000010
R1	0x00010B
R2	0x000235
R3	0x000302
R4	0x000400
R5	0x000500
R6	0x0006C4
R7	0x00078B
R8	0x000802
R9	0x000900
R10	0x000AC0
R11	0x000B00
R12	0x000C3B
R13	0x000D00
R14	0x000EC0
R15	0x000FC0
R16	0x001000
R17	0x001100
R18	0x001200
R19	0x00133F
R20	0x0014FF
R21	0x0015FF
R22	0x00163B
R23	0x0017D8
R24	0x0018D8
R25	0x001901
R26	0x001A0F
R27	0x001B55
R28	0x001C55
R29	0x001D00
R30	0x001E00
R31	0x001F00
R32	0x002000
R33	0x002105
R34	0x002205
R35	0x002334
R36	0x002403
R37	0x002500
R38	0x002611
R39	0x002702
R40	0x0028CE
R41	0x002900
R42	0x002ABF
R43	0x002B0F
R44	0x002C88
R45	0x002D88
R46	0x002E40
R47	0x002F41
R48	0x003060
R49	0x003161
R50	0x003200
R51	0x00331E
R52	0x00343E
R53	0x003502
R54	0x003600
R55	0x003700
R56	0x003800
R57	0x00396E
R58	0x003A00
R59	0x003B00
R60	0x003C00
R61	0x003D01
R62	0x003E00
R63	0x003F00
R64	0x004000
R65	0x004100
R66	0x004201
R67	0x004300
R68	0x004400
R69	0x004500
R70	0x004600
R71	0x004701
R72	0x004800
R73	0x004900
R74	0x004A00
R75	0x004B01
R76	0x004C3E
R77	0x004D00
R78	0x004E00
R79	0x004F00
R80	0x005000
R81	0x005178
R82	0x00525A
R83	0x005300
R84	0x005400
R85	0x005512
R86	0x005612
R87	0x005712
R88	0x005821
R89	0x005900
R90	0x005A02
R91	0x005B03
R92	0x005C33
R93	0x005D0F
R94	0x005E17
R95	0x005F05
R96	0x006002
R97	0x006103
R98	0x006244
R99	0x00630F
R100	0x006417
R101	0x006505
R102	0x006600
R103	0x006731
R104	0x0068FE
R105	0x0069B8
R106	0x006A5A
R107	0x006B4E
R108	0x006CCA
R109	0x006D03
R110	0x006E00
R111	0x006F01
R112	0x007000
R113	0x007100
R114	0x007200
R115	0x007300
R116	0x007400
R117	0x007500
R118	0x0076FF
R119	0x0077FF
R120	0x0078FF
R121	0x0079FF
R122	0x007AFF
R123	0x007B02
R124	0x007C02
R125	0x007D00
R126	0x007E01
R127	0x007F01
R128	0x008077
R129	0x008100
R130	0x008239
R131	0x008349
R132	0x008433
R133	0x00853C
R134	0x0086CF
R135	0x00879D
R136	0x008803
R137	0x008900
R138	0x008A01
R139	0x008B00
R140	0x008C00
R141	0x008D00
R142	0x008E00
R143	0x008F00
R144	0x009000
R145	0x009169
R146	0x009233
R147	0x00933C
R148	0x0094CF
R149	0x00959C
R150	0x009600
R151	0x009702
R152	0x009800
R153	0x009901
R154	0x009A01
R155	0x009B77
R156	0x009C00
R157	0x009D00
R158	0x009E00
R159	0x009F0D
R160	0x00A029
R161	0x00A100
R162	0x00A20D
R163	0x00A329
R164	0x00A400
R165	0x00A575
R166	0x00A605
R167	0x00A700
R168	0x00A875
R169	0x00A900
R170	0x00AA00
R171	0x00AB00
R172	0x00ACEF
R173	0x00AD00
R174	0x00AE00
R175	0x00AF00
R176	0x00B009
R177	0x00B1A3
R178	0x00B292
R179	0x00B3DB
R180	0x00B4EA
R181	0x00B529
R182	0x00B633
R183	0x00B755
R184	0x00B8F0
R185	0x00B980
R186	0x00BA11
R187	0x00BB95
R188	0x00BC15
R189	0x00BD01
R190	0x00BE19
R191	0x00BF01
R192	0x00C001
R193	0x00C100
R194	0x00C200
R195	0x00C3A4
R196	0x00C400
R197	0x00C500
R198	0x00C622
R199	0x00C700
R200	0x00C800
R201	0x00C922
R202	0x00CA00
R203	0x00CB00
R204	0x00CC22
R205	0x00CD0E
R206	0x00CE00
R207	0x00CF00
R208	0x00D04D
R209	0x00D100
R210	0x00D200
R211	0x00D31A
R212	0x00D400
R213	0x00D500
R214	0x00D61A
R215	0x00D700
R216	0x00D800
R217	0x00D91A
R218	0x00DA00
R219	0x00DB00
R220	0x00DC6E
R221	0x00DD00
R222	0x00DE78
R223	0x00DF00
R224	0x00E06E
R225	0x00E100
R226	0x00E278
R227	0x00E300
R228	0x00E46E
R229	0x00E500
R230	0x00E678
R231	0x00E700
R232	0x00E86E
R233	0x00E900
R234	0x00EA78
R235	0x00EB00
R236	0x00EC00
R237	0x00ED17
R238	0x00EE70
R239	0x00EF00
R240	0x00F000
R241	0x00F11E
R242	0x00F284
R243	0x00F380
R244	0x00F400
R245	0x00F54F
R246	0x00F679
R247	0x00F70E
R248	0x00F800
R249	0x00F91E
R250	0x00FA84
R251	0x00FB80
R252	0x00FC00
R253	0x00FD4F
R254	0x00FE79
R255	0x00FF0E
R256	0x010000
R257	0x01011E
R258	0x010284
R259	0x010380
R260	0x010400
R261	0x01054C
R262	0x01064B
R263	0x010740
R264	0x010800
R265	0x01091E
R266	0x010A84
R267	0x010B80
R268	0x010C0D
R269	0x010D0D
R270	0x010E0D
R271	0x010F0D
R272	0x011000
R273	0x011198
R274	0x011296
R275	0x011380
R276	0x011400
R277	0x011598
R278	0x011696
R279	0x011780
R280	0x011800
R281	0x011998
R282	0x011A96
R283	0x011B80
R284	0x011C00
R285	0x011D98
R286	0x011E96
R287	0x011F80
R288	0x01203F
R289	0x01213F
R290	0x01223F
R291	0x012300
R292	0x012421
R293	0x012580
R294	0x012600
R295	0x012700
R296	0x012803
R297	0x012921
R298	0x012A80
R299	0x012B00
R300	0x012C00
R301	0x012D03
R302	0x012E3B
R303	0x012F0A
R304	0x013000
R305	0x013100
R306	0x013200
R307	0x013301
R308	0x013400
R309	0x013501
R310	0x013600
R311	0x013700
R312	0x013800
R313	0x013900
R314	0x013A00
R315	0x013B00
R316	0x013C00
R317	0x013D00
R318	0x013E06
R319	0x013F8B
R320	0x014000
R321	0x014100
R322	0x014200
R323	0x014305
R324	0x014400
R325	0x0145A0
R326	0x014604
R327	0x014700
R328	0x014802
R329	0x014943
R330	0x014A00
R331	0x014B00
R332	0x014C00
R333	0x014D1C
R334	0x014E00
R335	0x014F00
R336	0x015002
R337	0x015100
R338	0x015200
R339	0x015301
R340	0x015400
R341	0x015500
R342	0x015600
R343	0x015700
R344	0x015800
R345	0x0159A1
R346	0x015A00
R347	0x015BA1
R348	0x015C03
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     > Powering down APLL1, and disabling output 7, and loading that .tcs (no runscript ran at any point) DPLL2 cannot lock, is that correct? This is the part that doesn't make any sense as we shouldn't be impacting anything on DPLL2..

    We tried to load the last .tcs file you sent us, that one with APLL1 and out 7, no runscript .

    The system can’t lock, LOPL and LOFL are set, sometimes LOFL is cleared, but during our tests we have never seen LOPL cleared.

     

    >What happens if you go through GUI and update rather than load the .tcs file I provided. So start with working config (APLL1 and CH7) active. And step by step go through power down CH7, disable CH7 and finally Powerdown PLL1. At which step, does OUT0 coming >from DPLL2 lose frequency and/or status of DPLL2 show holdover. 

    We are running the tests you have suggested

     

    >With regards to the working configuration not working on your board. I'm assuming at no point the reference DPLL locked, correct?

    That’s correct.

     

    > Was it reading the reference as valid and DPLL just not locking, or was reference never valid?

    PPS reference was valid

     

    > Next was the frequency error, the 10.0021xx MHz any different when you were using your TCXO vs connecting the TCXO from our EVM? Also, if you can perform a register dump and send that file, I can look at it. 

    No difference. Attached the register dump.

     

    Regards,
    Michele

  • 0 in reply to Michele Pedroni
    TI__Expert 6140 points

    Hi Michele, 

    Thanks for the details. How did the testing go in manually updating the .tcs after starting with the APLL1/DPLL1, APLL2/DPLL2, CH7 active configuration. 

    Your note above also said: "The system can’t lock, LOPL and LOFL are set, sometimes LOFL is cleared, but during our tests we have never seen LOPL cleared." I'm assuming this implies LOPL2 and LOFL2. As once we disable APLL1, LOFL1 and LOPL1 will be set since DPLL1 is now powered down essetially. 

    On your board, what's being used into the reference input for the reference DPLL is the exact same as what was used on the EVM that was able to get the REF DPLL locked? 

    I'm requesting lab time for this week to see if I can review the config with just CH0 and DPLL2 active and get expected results on EVM. 

    Thanks and regards, Amin 

  • 0 in reply to Amin Eshraghi
    Prodigy 100 points

    Hello Amin,

    following your suggestions to disable one by one the unused output and the APLL1 we finally have a working configuration on the EVM.

    The sequence that worked for us was disabling APLL1 first and after that CH7.

    We have performed a large number of tests and the system appears to be reliable.

    >I'm assuming this implies LOPL2 and LOFL2. As once we disable APLL1, LOFL1 and LOPL1 will be set since DPLL1 is now powered down essetially. 

    Exactly.

    The problem remains on our hardware. We use exactly the same configuration loaded in the EVM and the same I2C line.

    We tried to connect the EVM's clocks (Xo and TCXO) on our hw but the behavious is the same.

    Have you noticed something suspicious in the registries I sent you?

    Thanks!

    Regards,

    Michele

  • 0 in reply to Michele Pedroni
    TI__Expert 6140 points

    Hi Michele, 

    Can you probe the IN0 input on the evm vs on your board and see if there are any issues with signal integrity? Any noise on the 1 pps input can be problematic, and unfortunately there are cases where it clears the "reference valid" but REF DPLL still cannot lock. 

    A differential signal on IN0 will also work better, as it will have better noise immunity.  You can change the "interface type" in step 2 accordingly, note a run script is not needed. 

    Another suggestion, noise from SPI can cause problems. I know you're using I2C, but if we can disconnect those lines, that can be another thing to try. 

    If you give me a register dump of the EVM with your new configuration (APLL1/DPLL1/CH7 disabled) and one from your board, it will be easier to directly compare. If possible, I would like 3 of them: 

    - EVM: reference is valid, but DPLL2 still hasn't locked (LOPL2 and LOFL2), so about ~1 minute after startup? 

    - EVM: reference valid and DPLL2 locked, so ~few minutes after startup? 

    - Your board: reference valid and DPLL2 not locked, ~few minutes after startup (same as case above) 

    Thanks and regards, Amin 

  • 0 in reply to Amin Eshraghi
    Prodigy 100 points

    Hello Amin,

     we finally have our working hardware, I have matched the impedance of the clock lines and now our board works as EVM (even though the XO frequencies are different, 48Mhz ours and 48.0048 the EVM).

     To set the right XO frequency (48Mhz), we should modify the XO field and make a runscript.

     Since you told me that you manually changed some parameters after the runscript, could you please tell me which parameters I have to edit after the runscript?

     Thanks!

    Regards,

    Michele

  • 0 in reply to Michele Pedroni
    TI__Expert 6140 points

    Hi Michele, 

    After runscript, please perform the follow: 

    - Disable: DPLLx_HOLDOVER_MODE

    - Enable: DPLLx_FASTLOCK_ALWAYS

    - Disable: DPLLx_TDC_TCXO_DLY_GEN_EN

    (should be optional): 

    - Disable: DPLLx_REF_HIST_HOLD

    - Disable: DPLLx_REF_HIST_EN 

    You're using DPLL2 only so all the above should be on DPLL2. 

    Thanks and regards,

    Amin 

  • 0 in reply to Amin Eshraghi
    TI__Expert 6140 points

    Hi Michele, 

    One more thing that I forgot to mention, please increase the phase detect threshold. Increase the lock and unlock until it's at a minimum same order of magnitude as below. 

    Thanks and regards,

    Amin 

  • 0 in reply to Amin Eshraghi
    Prodigy 100 points

    Hello Amin,

    thanks for supporting us.

    Now the system works as expected!

    Regards,

    Michele

  • 0 in reply to Michele Pedroni
    TI__Expert 6140 points

    Hi Michele, 

    I'm glad to hear that. It took a while but we got there. 

    Amin