Other Parts Discussed in Thread: LMK04828, DAC38J84EVM
Tool/software: WEBENCH® Design Tools
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Tool/software: WEBENCH® Design Tools
Hello Shivaprasad,
1. You are not getting the correct output because divide of one is an odd divide, and you must enable duty cycle correction for odd divides. Set DCLKout0_MUX, DCLKout2_MUX, and DCLKout10_MUX = 0x01 (Divider+DCC+HS).
2. How are you measuring the 100MHz output? Are you using a balun, or have you terminated the unused leg of the differential pair to 50Ω?
Can you tell me what synchronization procedure you are following? Note that section 9.3.3.1 of the datasheet explains the process of using the fixed digital delay to achieve a known phase offset between the outputs.
Regards,
using 1 point i will follow and tell you result.
I measured by adding 50ohm to the output in spectrum analyzer.
I have one more dought : i'm not getting smooth pulse it is some distorted, you can see that 2 screenshot of spectrum analyzer.
Thanks &Regarde
Basavakiran
Hello Basavakiran,
To confirm, you are referring to the distortion in this image:
Typically when I see this kind of distortion it has two common causes:
Regards,
Hi Derek Payne,
after adding 50ohm to the differential another end, I got little bit Smooth Output Signal,
thanks for helping to solve my problem. I have one more dought
I want to program LMK with the help of Xilinx KC705 FPGA, how to connect and how to program LMK
Thanks & Regards,
Basavakiran
Hello Basavakiran,
After confirming your desired settings in TICS Pro, you can use TICS Pro to export hex register values:
You can store the hex register programming in FPGA memory or read it in from some other external device. The register programming interface is a SPI bus which supports bidirectional read/write, see Figure 1 in the datasheet for the timing diagram.
For writing to the device, the SCK, CS*, and SDIO pins should be connected to FPGA SPI clock, chip select, and MOSI nets respectively. For reading from the device, you can either use a bidirectional transmitter on the MOSI net and switch to receive mode for SPI reads as the data bits are transmitted, or you can use 4-wire SPI mode by configuring one of the GPIO pins (PLL1_LD, PLL2_LD, CLKin_SEL0, CLKin_SEL1, or RESET pin) for SPI readback, and connecting the readback pin to the FPGA MISO line.
Regards,
Hi Derek Payme,
I used KC705 Xilinx FPGA in that I taken from XADC pins, from that i got Vp-p as 5 Volts, bt from LMK Vp-p was 2.2 Volts
so from which pins of FPGA have to use for connecting LMK.
Thanks & Regerds,
Basavakiran
Hello Basavakiran,
The LMK04828 I/O levels are 3.3V. While I don't have access to the schematics or EVM documentation (Xilinx requires login for this information), generally you have a few options for communicating with any FPGA:
Regards,
Hi Derek Payne,
I got output clocks but those are not in SYNC and default it is taking as Divider value as 2(means External input clock is 100MHz then I'm getting output clock was 50MHz) but i want divider value should be 1(I/P clock 100MHz, O/P clock 100MHz).
How should i program DCLKout10_MUX = 0x01 (Divider+DCC+HS) and SYNC Divier - selection.
I you tell me register address and value, some solution for this dought.
Thanks & Regards
Basavakiran
Hi Basavakiran,
The value of the DCLKout10_DIV (0x128[4:0]) should be set to 0x01 to ensure the divider value is 1. DCLKout10_MUX = 0x01 is correct for this mode.
You must follow the SYNC procedure outlined in the datasheet in order to align the outputs. Paraphrased, this looks like:
I have included a TICS Pro profile which accepts 100MHz on CLKin1 and should generate 100MHz on DCLKout0, SDCLKout1, DCLKout2, and DCLKout10.
LMK04828 100MHz in, 100MHz out.tcs
Regards,
Hi Derek Payne,
I'm getting 40ps delay in between DCLKout0, DCLKout2, and DCLKout10. i Changed DCLKoutX_DDLY_CNTH and DCLKoutX_DDLY_CNTL register value also but there is no changes in that delay, what should i do?
can I do Same procedure for DAC038J84EVM? DAC Mode (LMFS=4211).
Thanks & Regards
Basavakiran
Hi Basavakiran,
Each time you change the delay values (DCLKoutX_DDLY_CNTH/L), you must re-synchronize the LMK04828.
As far as I know, DAC38J84EVM is designed for use with the HSDC Pro software, which has its own configuration files included for LMK04828 based on DAC LMFS mode, and which uses the TSW14J56EVM to manage the synchronization procedure. That said, you could manually program the LMK04828, in which case the procedure described above would be applicable.
If you have further questions on DAC34J56EVM I recommend opening a separate E2E question specific to that EVM. The DAC team can offer more support for their EVM configurations and procedures.
Regards,
Hi Derek Payne,
Thank you so much for helping me and suggesting
Thanks & Regards
Basavakiran Hiremath
Hi Derek Payne,
External Clock to the LMK04828 (CLKin_1 = 100MHz), I need DCLKout0=100MHz,DCLKout2=300MHz and DCLKout10=2400MHz with all outputs are get SYNC.
Please can you send me step wise PPT with Screenshot of LMK GUI(TICS Pro).
Thanks and Regards
Basavakiran
Hi Derek Payne,
Nice PPT I understood easily NO confusion after seeing PPT.
I'm getting 100MHz, 300MHz and 2400MHz when I used VCO0 that time it's not taking External Clock, it's taking on board clock, but i want to Generate with external 100MHz input clock not on board.
Take External Input Clock(100MHz) then Generate 100MHz and 2400MHz.
the Output of LMK should Depends on External Input (100MHz).
After getting output can you share me "CLKin and PLLs" Window and Remaning Windows Screenshot PPT.(same as previous format)
Thanks & Regards
Basvakiran
Hi Basavakiran,
On the LMK04828, CLKin0/CLKin1/CLKin2 are connected as inputs only to PLL1. In order to get an external clock at 100MHz on CLKin1 to produce the desired signals, you will need to use PLL1 and drive a VCXO.
However, if your 100MHz signal is low-noise, you could instead directly drive the OSCin port. That way PLL1 is not required, and you do not need to use an external VCXO if you do not need one.
In the attached PPT below, I've included both options for your consideration. I did not go over the holdover page because it is not critical to operation, we can revisit the holdover page if it is needed. I also did not go over the "Other" page, because the I/O settings on this page are straightforward.
I've also attached the TICS Pro file I used to generate the configurations for PLL1+PLL2 option. The powerpoint explains how to modify the PLL1+PLL2 configuration to use PLL2 only.
Regards,