LMK05318: Output frequency present even when Reference Inputs are not driven- Need Clarification.

Sathiya Seelan Sekar1

Part Number: LMK05318

Hi,

We are using LMK05318RGZT in our board and it is in testing.

What we found is we are getting clock frequency at the output even when we don't drive any of the Reference clock Inputs.

We have 48MHZ on board XO that drives the XO input of the LMK05318.

We do not want the output clock present when there is no Reference inputs (Primary/ Secondary) to DPLL.

Please help us to program the IC for this requirement.

I understand that the Hold over & Free run feature is what producing the output frequency even when there is no Reference Inputs.

Can you help us in programming the IC such that output clock should present only when we drive any of the reference input to DPLL.

Appreciate your earliest help in this regard.

Thanks & Regards,

Sathiya Seelan Sekar

over 3 years ago

0 Derek Payne over 3 years ago

TI__Mastermind 29010 points

Hi Sathiya,

In register R29 (0x1D), bits 1 and 2 are MUTE_DPLL_FRLOCK and MUTE_DPLL_PHLOCK, which will mute the outputs until the DPLL detects frequency lock or phase lock, respectively. These must be used in conjunction with the CHx_MUTE_LVL settings.

Regards

0 Sathiya Seelan Sekar1 over 3 years ago in reply to Derek Payne

Prodigy 160 points

Hi Derek Payne,

Thank you for the update, but i still need clarity in Register R25 setting.

We are using channel 0 in HCSL output format & channel 5 in CMOS output using only P in the pair and not using the remaining channels.

My doubt is, when we set the CHx_MUTE_LVL settings through Register R23, do we need to enable the Mute Control Register R25 for the Output channel 0 & 5 to make the settings effect?

Please clarify.

Thanks & Regards,

Sathiya Seelan Sekar

0 Derek Payne over 3 years ago in reply to Sathiya Seelan Sekar1

TI__Mastermind 29010 points

Hi Sathiya,

Yes, CH0_MUTE and CH5_MUTE must be enabled.

Regards,

0 Sathiya Seelan Sekar1 over 3 years ago in reply to Derek Payne

Prodigy 160 points

Thank you Derek Payne for you earliest response.

We will test the board & update the feedback.

0 Sathiya Seelan Sekar1 over 3 years ago in reply to Sathiya Seelan Sekar1

Prodigy 160 points

Hi Derek Payne,

We are yet to implement your suggestion but have few queries that need your clarification.

I have a doubt in the Free Run and Hold Over feature supported by LMK05318.

For DPLL mode of operation, It is mentioned in Data Sheet that, after Power On reset,

"APLL1 locks the VCO1 frequency to the external XO input and operates in free-run mode. Once a
valid DPLL reference input is detected, the DPLL begins lock acquisition."

I understand, the PLL1 locks to external XO input first and operate in free-run mode to provide output clocks.

Next or In parallel, the DPLL lock acquisition begins. It will take some time to lock the PLL1 with (Primary / Secondary) present Reference Input and produce the clock outputs synchronized to these reference input.

But our requirement is such that, we never want clock at any of the outputs using Free run or Hold over Mode.

In detail, We want to disable CLK0 and CLK5 output channels to take input from crystal XO when there is no Primary/secondary clocks are present.

We want CLK0/CLK5 channels to operate only from primary/secondary clocks but not from crystal input.

we will have either primary/secondary reference clock present in board and we should be getting CLK0 & CLK5 output using that only and the moment primary/secondary clock is gone or invalid, LMK05318 should not take clock from crystal and feed the CLK0/CLK5 output.

At present we are getting clock even when there is no primary/secondary clocks.

Our initialization requirement is like below,

After the Board Power ON, LMK05318 should drive output clock only when the Primary or Secondary reference clock is present.

Should not use External XO input to provide output clocks at any point of time.

When the reference input to DPLL became missing or invalid, then LMK05318 should stop driving all of the output clocks.

Please let me know if the DPLL PHASE & FREQ Mute configuration settings as suggested by you in our previous thread discussion is sufficient for this requirement OR

we have option to disable the Free Run & Hold Over Mode to achieve this requirement?

Please help us at the earliest possible to proceed with our testing.