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TPL5010: TPL5010

Part Number: TPL5010

Hi

I have a question about manual rest pin for TPL5010.

After start-up (normal operation), if DELAY/M_RST is asserted to high, RSTn will generate a low signal after delay tM_RST.

If DELAY/M_RST remain high signal, how about RSTn work? stay low or assert high after delay tDB+tRSTn.

BRs

 

 

  • Hi Mark,

    My coworker will get back to you tomorrow.

    Regards,
    Hao

  • See Figure 10 in the datasheet; t_DB starts at the falling edge of the DELAY/M_RST signal. If DELAY/M_RST remains high, then RSTn will be held low (if a valid M_RST pulse was issued).

    Note that if DELAY/M_RST is connected to VDD at startup, this is interference with the resistance reading; the device will not be able to select the time interval until VDD is removed from the pin.

    Kind regards,
    Lane