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How much jitter do logic chips add?

Prodigy 60 points

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Hi,

Does anyone have any idea how much jitter is added by logic chips? I have a 16 MHz sample clock driving an ADC, but I want to have it MUXed so users can select an external synchronization clock if they are able to provide one. The period jitter for my requirements must be below 10 psRMS. The jitter contributed by the oscillator I am using is 5 psRMS.

I've looked a chips like LMK00804B-Q1, but these have one LVDS input, and one CMOS input. It also features a 4 x fanout.

I wouldn't necessarily be against using a chip like this as:

  • Even although the I expect the external clock trace to be extremely short, I wouldn't be against requiring the external clock to be LVDS if it meant an easier solution.
  • The fanout isn't necessarily unworkable either, as my clock goes to multiple destinations, but this is a bit overkill as all the clocked parts are extremely close and transmission line effects will probably not be a problem. Once again, I wouldn't be against using a fanout buffer if it meant an easier solution.

However, the LMK00804B-Q1, for example, uses 36 mA, is a costly, and I suspect overkill for my application, where all I want is a single 2:1 MUX that has jitter specs listed in the datasheet. I'm wondering if something simpler, like a fast logic MUX (SN74LVC2G157) would be sufficient. It costs about 10% the cost, and uses basically no power other than the dynamic switching current.

Thanks for any advice.

  • Hi,

    Unfortunately, we don't test that for our devices so I wouldn't have any values to provide. However, there is an EVM that can support that device if you are able to run jitter tests of your own to get an idea.

    Check out our new AXC family of Voltage Translators! 

    Watch the Introduction to AXC Family to find out more about the family.

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