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LMH1983: PLL1 not LOCKIN

Kazuki Itoh
Genius 9175 points
Part Number: LMH1983

Hi team,

1080i, 59.94 Hz horizontal synchronization created from a fixed oscillator (27 MHz) is input to HIN after power up.

The register settings are the device default settings.
When the HIN is input, the NO_LOCK pin is supposed to be  L . But in some boards, NO_LOCK does not go to L.

Since NO_LOCK is monitoring the status of PLL 1 through 4, I read the status register.
PLL 2, 3, and 4 were locked but PLL1 was not locking.

Is it correct that only the HIN input is needed for PLL1?
There was no change when I put VIN for testing.
I checked the external 27M-VCXO is working.

Best Regards,

Itoh

  • 0
    TI__Mastermind 18070 points

    Hi Itoh,

    My coworker will get back to you tomorrow.

    Regards,
    Hao

  • 0
    TI__Expert 6140 points

    Hi Itoh, 

    Please make sure LockStepSize and Loss of Lock Thresholds are set. Is there a lot of jitter on reference? That could explain what's happening. I've copied the relevant section from the datasheet below. 

    Thanks and regards,

    Amin 

    8.3.6 Lock Determination

    There are four bits in Register 0x02 that indicate the lock status of the four PLLs. Lock determination for PLL1 can be controlled through two registers: LockStepSize (Register 0x2D) and Loss of Lock Threshold (Register 0x1C). The LockStepSize register sets the amount of variation that is permitted on the VC_LPF pin while still considering the device to be locked. If the reference to the LMH1983 has a large amount of jitter, then the device may be unable to declare lock because the LockStepSize is set too low. The second register, the Loss of Lock Threshold register, controls the lock state declaration of PLL1. This register sets a number of cycles on the HIN input that must be seen before loss of lock is declared. For some reference signals, there can be several missing HIN pulses during vertical refresh. Therefore, it is suggested that this register be loaded with a value greater than six (Loss of Lock Threshold > 6). Pin 11, NO_LOCK, gives the lock status of the LMH1983. Note that the status of the NO_LOCK pin can also be read from Register 0x01, and it is a logical OR of the four individual NO_LOCK status bits of the four PLLs. The NO_LOCK status pin is masked by the bits in the PLL Lock mask (Register 0x1D), and the status is also masked if an individual PLL is powered down.