LMK05318: Output sync with PRIREF or SECREF below 100kHz

Prodigy 60 points

Replies: 4

Views: 32

Part Number: LMK05318

Hi all,

I'd like to get an output clk locked with SECREF,   I use the  TICS-Pro to generate reg settings, now I let,

XO=24.576MHz (50ppm), SECREF=1Hz-1MHz(from Agilent 33210A Waveform Generator), OUT7 = SECREF * 10

It works well for input freq large 100kHz, the output7 sync with the input.

It doesn't work for input below 100kHz, the output7 freq is right, but doesn't sync with input, is there anything I should pay attention?



4 Replies

  • Genius 10640 points

    Hi Jiahua,

    My coworker will get back to you by the next business day.


    Clock and Timing Systems & Applications

    To view training videos on Clock and Timing Solutions please visit  TI Precision Labs ​​​​

    More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html

  • Hi Jiahua, 

    What information are you relying on in order to confirm "it works well" or passes for above 100 kHz and similarly not working for below 100 kHz? When Out7 is in "sync" with reference are you judging their phase or more that a shift in frequency on the reference input causes a shift on the output? 

    Reading the status signals to understand what's happening is always good start for any debugging. 

    Thanks and regards,


    R14 and R13

  • In reply to Amin Eshraghi:

    Hi Amin,

    In my application, I have a secref input(1Hz-1MHz), I need a output7(=secref*10) which locked with the secref input.

    I let STAT0 pin output DPLL R Divider, STAT1 pin output DPLL FB Divider.

    For secref above 100kHz, STAT1 is in sync with STAT0, they have a fixed phase of 0 or 180 degree. That meas the output7 is also synced with secref. right?

    For secref below 100kHz(for example 10Hz), Both of STAT1 and STAT0 have a correct freq of 5Hz, but the phase between them is always in judging, the DPLL is always in unlock status. I have no idea why?

    Attached is my TICS Pro file.



  • In reply to JiaHua Wang:

    Hi Jiahua, 

    Monitoring the DPLL R divider and FB divider path will let you know if DPLL has locked. 

    The attached config is for 10 Hz, was a runscript run?

    The status page doesn't seem to be updated (as everything is checked) so I'm not sure, were either reference considered valid? 

    Also why is VCO1 freq not 2.5 GHz?