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LMK04826: Synchronization of Different LMK04826's

Part Number: LMK04826
Other Parts Discussed in Thread: LMK04832

Hi

In my custom Board, I am having 2 LMK04826's and 4 JESD ADC's

I am using these LMK's for JESD Synchronization.

Now LMK 1 output is connected as input to LMK 2.

So to achieve JESD Synchronization, first I need to Synchronize two LMK's

1. Can It be done by toggling the SYNC_POLL bit ??  (or)

2. I need to use 0 Delay mode ??

How to achieve LMK Synchronization ??

What is the use of 0 Delay Mode ??

  • Hi there,

    My coworker will get back to you next Monday.

    Regards,
    Hao

  • Hello Pavan,

    Please take a look at this Multi-Clock synchronization app note and this thread.  It will help to explain the 0-delay and synchronization.

    The simplest way it to use zero delay mode with a reference the same frequency as the SYSREF.  Then the SYSREF and all clock frequencies will be aligned.

    Do you require the SYSREF pulse to occur at only on the LMFC frequency multiple as per JESD204B spec, or also at the exact same moment at the two devices?

    73,
    Timothy

  • Hi

    I need SYSREF pulse only on the LMFC Frequency multiples .

    Why to use sysref as feedback clock ??  Any benefit of using sysref over DClk_out_6  / Dclk_out_8 ??

  • Hello

    I am working on Synchronization of 2 LMK's

    LMK = LMK04826B

    VCO  Frequency = 2500MHz

    One of the output from first LMK is driving second LMK .

    1. First LMK -- I am configuring in Single Loop Mode .

        As my input is connected to OSCin. Also I am not having any external Loop filter. So  I can't use PLL 1  Is it correct ??

    2. Second LMK -- I am configuring it in Zero Delay Single Loop Mode

        Input (OSCin) is 100 MHz

        DCLK_out_0   is 156.25 MHz.

        SDCLK_out_1 is 4.88 28125 MHz 

        Feedback_clk is  Dclk_out_6 = 156.25 MHz 

        I have attached the configurations for LMK 2 

        Can you please verify these configurations ??

        or else send the configuration file for these specs .

        It will be helpful for me, to know where I am going wrong.

    3. Can I use DCLK_out_6 as feedback Clk ??

        You have suggested to use sysref as feedback clk      

    Thanks 

    LMK_zero_delay_config.tcs

        

    LMK_zero_delay_config.txt
    R0 (INIT)	0x000090
    R0	0x000010
    R2	0x000200
    R3	0x000306
    R4	0x0004D0
    R5	0x00055B
    R6	0x000600
    R12	0x000C51
    R13	0x000D04
    R256	0x010010
    R257	0x010155
    R258	0x010255
    R259	0x010301
    R260	0x010422
    R261	0x010500
    R262	0x0106F0
    R263	0x010755
    R264	0x010808
    R265	0x010955
    R266	0x010A55
    R267	0x010B01
    R268	0x010C22
    R269	0x010D00
    R270	0x010EF8
    R271	0x010F55
    R272	0x011008
    R273	0x011155
    R274	0x011255
    R275	0x011301
    R276	0x011422
    R277	0x011500
    R278	0x0116F8
    R279	0x011755
    R280	0x011810
    R281	0x011955
    R282	0x011A55
    R283	0x011B01
    R284	0x011C22
    R285	0x011D00
    R286	0x011EF1
    R287	0x011F11
    R288	0x012010
    R289	0x012155
    R290	0x012255
    R291	0x012301
    R292	0x012422
    R293	0x012500
    R294	0x0126F8
    R295	0x012711
    R296	0x012810
    R297	0x012955
    R298	0x012A55
    R299	0x012B01
    R300	0x012C22
    R301	0x012D00
    R302	0x012EF8
    R303	0x012F11
    R304	0x013019
    R305	0x013155
    R306	0x013255
    R307	0x013301
    R308	0x013402
    R309	0x013500
    R310	0x0136F9
    R311	0x013701
    R312	0x013820
    R313	0x013903
    R314	0x013A02
    R315	0x013B00
    R316	0x013C00
    R317	0x013D08
    R318	0x013E03
    R319	0x013F11
    R320	0x01408B
    R321	0x014100
    R322	0x014200
    R323	0x014311
    R324	0x0144FF
    R325	0x01457F
    R326	0x014618
    R327	0x01471A
    R328	0x014802
    R329	0x014942
    R330	0x014A02
    R331	0x014B16
    R332	0x014C00
    R333	0x014D00
    R334	0x014EC0
    R335	0x014F7F
    R336	0x015003
    R337	0x015102
    R338	0x015200
    R339	0x015300
    R340	0x015478
    R341	0x015500
    R342	0x015678
    R343	0x015700
    R344	0x015896
    R345	0x015900
    R346	0x015A78
    R347	0x015BD4
    R348	0x015C20
    R349	0x015D00
    R350	0x015E00
    R351	0x015F0B
    R352	0x016000
    R353	0x016110
    R354	0x0162A4
    R355	0x016300
    R356	0x016400
    R357	0x016550
    R369	0x0171AA
    R370	0x017202
    R380	0x017C18
    R381	0x017D77
    R358	0x016600
    R359	0x016700
    R360	0x016819
    R361	0x016959
    R362	0x016A20
    R363	0x016B00
    R364	0x016C00
    R365	0x016D00
    R366	0x016E13
    R371	0x017300
    R8189	0x1FFD00
    R8190	0x1FFE00
    R8191	0x1FFF53
    

  • pavan kumar8 said:
    I need SYSREF pulse only on the LMFC Frequency multiples .

    Ok, that simplifies things.

    The simplest architecture would be to provide a frequency of 4.882 812 5 MHz as a reference input two separate LMK04826 devices.  Using SYSREF of each device as ZDM feedback, then all clocks related to the SYSREF frequency would be deterministic between the devices.  Whenever you requested SYSREF for either device, it would align with the LMFC as your requirement above.
       - Note if you wanted to output 100 MHz that was deterministic between the two LMK04826, you would need to provide a frequency lower than 4.8828125 MHz or pick a SYSREF frequency which works better with both 156.25 MHz and 100 MHz.  I notice in your config you sent over, you do have a 100 MHz.  However that is often for CPU clock and not phase critical and therefore ok to have variation.  To ensure 100 MHz, 156.25, and SYSREF were all deterministic, then the gcd(4.8828125, 156.25, 100) = 0.1953125 MHz.  Therefore a 0.1953125 MHz reference would need to be applied to the two LMK04826 devices!

    In this case, because the reference frequency is so low, the performance would not be as good as possible.  Using each device in dual loop mode with a higher VCXO frequency for jitter cleaning/PLL performance optimization would allow the best possible jitter performance.

    pavan kumar8 said:
    Why to use sysref as feedback clock ??  Any benefit of using sysref over DClk_out_6  / Dclk_out_8 ??


    SYSREF is typically the lowest frequency in the system.  The feedback clock needs to be operate at a frequency (or integer division) of the lowest frequency according to the GCD(input frequency, any output frequency which requires deterministic clocking).  The LMK04832 does support bigger divides on device clock dividers (up to /1023) and therefore DCLKout6 or DCLKout8 could actually be configured for SYSREF type frequencies and used for ZDM in an application such as yours, but there wouldn't necessarily be a clear benefit to using these outputs for ZDM except that it could allow a method to shift phase of all all the clocks of the downstream device relative to the input.

      - Consider the clock being used for ZDM will always have a phase locked with the reference input no matter the delay used on that clock.  The PLL will eliminate that phase adjustment programmed in.  However all the other clocks will shift relative to the feedback clock if you change for instance the DDLY.  Note the LMK0482x supports some PLL1_RDLY and PLL1_NDLY to adjust ZDM phase from input to output when using dual loop mode.

    pavan kumar8 said:
    1. First LMK -- I am configuring in Single Loop Mode .

        As my input is connected to OSCin. Also I am not having any external Loop filter. So  I can't use PLL 1  Is it correct ??

    That is correct.  Note it is still required to place a 2x capacitor and resistor in series to ground on PLL2 to complete it's external loop filter.  By our typical designation that's C1, C2, and R2.

    To use PLL1 you would connect your input to CLKinX, then have the VCXO connected to OSCin.

    pavan kumar8 said:

    2. Second LMK -- I am configuring it in Zero Delay Single Loop Mode

        Input (OSCin) is 100 MHz

        DCLK_out_0   is 156.25 MHz.

        SDCLK_out_1 is 4.88 28125 MHz 

        Feedback_clk is  Dclk_out_6 = 156.25 MHz

    These frequencies are not good for 0-delay because GCD(100 MHz, 156.25 MHz) = 6.25 MHz.   Not to mention the gcd of input to other clocks you'd like to have deterministic like SYSREF.

    Here is a solution for you to consider.  It is possible to run ZDM to keep just the device clock frequencies deterministic between the two devices, then use the SYSREF on the downstream device in re-clock mode.  The downstream device will then re-clock the SYSREF from the upstream device.  You need to adjust the timing so that the SYSREF input to CLKin0 is occuring at the falling edge of the OSCin signal to the downstream device.

    -- I recommend the LMK04832 device because the PLL2 phase detector frequency is able to run up to 160 MHz, so you wouldn't need to use a divide-by-2 on the downstream device and reduce the phase detector frequency to 78.125 MHz and could therefore get better phase noise performance.  The downstream device will have slightly worse performance due to the downstream cascade nature without using jitter cleaning.  The downstream device could introduce a VCXO to provide a clean reference at an optimum frequency.  In this case you would provide the input to CLKinX instead of OSCin.

    When connecting the SYSREF from the upstream device to the downstream device, DC couple and use HSDS 8 mA.  This provides a good common mode input voltage to the LMK input.

    73,
    Timothy