• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 2 answers
  • Subscribers 20 subscribers
  • Views 241 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LMX2594: questions when using PLLatinum Sim Tool

Hung Ching Hsu
Expert 3086 points
Part Number: LMX2594

Hi Team

My customer is using PLLatinum Sim Tool for LMX2594 simulation.

He has two questions when using it.

1. About Phase Margin

[Simulation condition]
Select device: LMX2594
Filter designer: Auto
Fpd: 200MHz
Fvco: 15000MHz

The customer said, the calculation result (Actual) is displayed as 70deg,

But from the bode plot between open loop gain and phase margin, the phase margin didn't seem like 70 deg.

When only look at peak value of phase margin, it looks close to 70 deg. So is that a bug that horizontal axis shifted?

Or "Actual" value of phase margin means just the peak value?


2. About LoopFilter Components C3

[Simulation condition]
Select davice: LMX2594
Filter designer: Fixed to LMX2594EVM constant value(forced component)
Fpd: 200MHz
Fvco: 15000MHz

There is an alert about loop filter component C3(the background becomes yellow).

After confirming the alert statement, it says "The capacitor closest to the VCO is less than 3.3nF, which could result in some degradation in VCO phase noise performance, and this is not modeled by the simulator".

Since the customer set the filter designer to "Fixed to LMX2594EVM constant value",
so the customer is wondering why the EVM would use a constant value like this even though it shows alert.

I am sorry but I am not familiar with PLLatinum Sim Tool, I tried to explain the question understandable.

If you need any other further information to solve the question, please just tell me. Thanks.

  • 0
    TI__Guru* 81400 points

    Hi Hung Ching,

    We will check with the developer of this tool and get back to you later. 

  • 0 in reply to Noel Fung
    TI__Guru* 81400 points

    Hi Hung Ching,

    1. I think the phase margin is correct, however the X-axis scale for open loop gain is not. We will fix this in next revision, thank you for bringing this up.

    2. This is fixed in the current revision, the min. capacitor value for C3 is not 1.5nF.

  • 0 in reply to Noel Fung
    TI__Expert 3086 points

    Hi Fung

    Thanks for your reply.

    Let me ask little more about it.

    1. I think the phase margin is correct, however the X-axis scale for open loop gain is not. We will fix this in next revision, thank you for bringing this up.

    →I got it. Is there an estimated date when the next revision will be released?

    2. This is fixed in the current revision, the min. capacitor value for C3 is not 1.5nF.

    →Is there any reason to fix C3 for 1.5nF in this revision?

    I appreciate your reply. 
    I'm asking this since the customer may have concern about this.
    Thanks
  • 0 in reply to Hung Ching Hsu
    TI__Guru* 81400 points

    Hi Hung Ching,

    1. I need to check again with the developer, as far as I know, we have regular time slot to maintain the tool.

    2. It was not mentioned in the datasheet, but it is required to put at least 1.5nF capacitor at the Vtune pin. If the capacitance is less than 1.5nF, the phase noise at around 100kHz offset will not be optimum.