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Part Number: LMK04828
I have used lmk04828b in our design on custom board, provided 100 mhz clock to OSC pin. I have already lmk evm kit. Lmk in our custom board not working when initiated through tics pro through the cable given part of kit. I have checked reset on board it is pulled low through 10k.
OSC clock we provided is coming out of OSC out of lmk, so clock input to lmk seems ok.
We try to program the devices through 3 wire SPI, no clock is coming out of dclk/sdlk.
At this point of time, I do not know what to check.
We did not bring the clk sel pins, it is kept open.
At cp out we are measuring 1.8 V.
Biasing to the chip and controls from tics pro seems ok, when we probed.
Thank-you for your initial debugging work.
Could your outputs be held in SYNC? This is programming dependent but can also be a function of pin 6, SYNC/SYSREF_REQ. My understanding is on POR default this should be low to allow outputs.
At POR you should also see ~315 MHz LVDS signals on CLKout4/6/8/10. -- Do you see this? SYNC pin as above could turn these outputs off.
Have you tested more than one of your boards?
When you say controls from TICS Pro seem ok, you are probing the SCK, SDIO, and CS* and confirm the clock, data, and chip select as expected?
To confirm programming independent of clock output, can you either toggle POWERDOWN and check for change in current draw to the device or...
- Power down --> Reg 0x002 = 0x01- Powered up --> Reg 0x002 = 0x00
or program PLL1_LD_TYPE between low and high (results in Status_LD1 pin changing state low/high).
- Low --> Reg 0x15F = 0x03- High --> Reg 0x15F = 0x04
More information Clock and Timing System products: http://www.ti.com/clock-and-timing/overview.html
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In reply to Timothy T:
Thanks for your input, i think we can rule out chip is bad.
Initially we have pulled the SYNC to high through resistor, now we have removed it.
As per your suggestion, we are getting around 319-315 MHz LVDS signals at CLKout4/6/8/10.
We have initially assembled only one board.
we will try the 3rd suggestion to check the programming side and come back to you.
here by attaching schematics for your reference.CS, SDIO & SCLK having 100E resistor series connected from FPGA.
In reply to Rajesh khanna:
Ok, let me know what your update is. Any chance another board will be assembled in the near future?
Also, could you re-try attaching the schematic? I don't see it.
We found the CS line to have more noise. trying to provide a pullup and decap to see whether it can solve the problem.
Please find the lmk sch. Another board will be assembled in a week time.
Ok, keep me posted on your progress. If you are able, please also attach a scope plot of a register programming with the SCLK, SDIO, and CS* lines.
Thanks for your help. After addressing CS line. We are able to get the device working.
I have one more problem now. We are getting the required clocks output on the device as per our design.
The lock output for both the PLL1 and PLL2 is not coming out. Register Settings are as follows
0x15F - 0x0B
0x16E - 0x13
When we try
0x15F - 0x04 -- LED is glowing outside
0x16E - 0x04 -- LED not glowing.
Pls give any suggestions.
I presume toggling between 0x1F5 = 0x04 and 0x1F5 = 0x03 results in the LED turning on and off?
If the LED cathode is connected to ground and the anode to the Status_LD2 output pin (with appropriate current limiting resistor), then 0x16E = 0x04 should result in an LED turned on. If the LED were flipped, the LED status would be off. Does toggling between 0x16E = 0x04 and 0x16E = 0x03 result in the LED turning on and off?
As I understand you are locked and on frequency by your measurements... Now that you are programming the device, can you confirm the CPout1 and CPout2 voltages are centered?
What is the phase detector frequency of PLL1? If you have a very low phase detector frequency the input impedance of some VCXOs will cause enough leaking for the device to think it is not locked because the charge pump has to work so hard to keep it on frequency.
Can you confirm the phase detector frequencies and PLL1_WND_SIZE and PLL2_WND_SIZE values? These registers are on the User Control page under PLL. If you have a high PLL1 phase detector frequency, you may need to reduce PLL1_WND_SIZE. PLL2_WND_SIZE should be = 2 (3.7 ns).
We haven't heard from you in a while, so I'm marking the thread as resolved for now. Please let us know if you still need assistance.
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