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LMK04208: Input sinwave 10MHz with slew rate of out range

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Replies: 5

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Part Number: LMK04208

Hi all


Would you mind if we ask LMK04208?

We have the question which is relation to following forum;
https://e2e.ti.com/support/clock-and-timing/f/48/p/923870/3413893

If the slew rate of input sinwave 10MHz is out of range,
-can the device regard as input?
-If the device regard as input, does jitter increase?

Kind regards,

Hirotaka Matsumoto

  • hi Matsumoto-san,

    with 10MHz sinewave, I have seen that PLL1 will not lock at all. 

    Since the loop bandwidth in PLL1 is very small, PLL1 output jitter is virtually equal to the jitter of the VCXO, so jitter will not get hurt with sine wave 10MHz reference clock, if it lock.

  • In reply to Noel Fung:

    Noel san

    Thank you so much for your reply!

    with 10MHz sinewave, I have seen that PLL1 will not lock at all. 
    ->If reference clock is 10MHz, could you inform us why the device(LMK04208) can't lock?
       Exactly, slew rate is out range.However, as our imagination, we assume that the device can lock. 
      

    Kind regards,

    Hirotaka Matsumoto

  • In reply to Hirotaka Matsumoto:

    hi Matsumoto-san,

    The R-divider is a counter, when it sees a rising edge, it will count. When slew rate is bad, the rising edge is not obvious, the counter may count at different time on the edge. As a result, the counter output is not a periodic clock with constant period and therefore leading to PLL unlock. 

  • In reply to Noel Fung:

    Noel san

    Thank you so much for your reply!

    OK, we got it!
    In case of Input sinwave 10MHz, is there the device which is fatisfied with sinwave 10MHz input?
    We assume that there are no devices.


    Kind regards,

    Hirotaka Matsumoto

  • In reply to Hirotaka Matsumoto:

    PLL1 unlock

    Caused by slow slew rate:

    1,Try to use a sinewave 10 MHz from an signal source instrument. Increase amplitude to double check lock status. Be careful not to violate max input limitation.

    If you can find PLL1 locked, then the key cause is from slew rate. --- Then you will add an Operation Amplifier with Schmitt trigger.

    Caused by a big VCXO current leakage:

    2, Send your TICS Pro configuration file. For PLL1 unlock, we need to consider VCXO leakage current with small phase detect frequency, charge pump and .VCXO input impedance.

    Caused by a noisy reference (10 MHz)

    3, Change to a clean reference, or increase loop bandwidth (limited by max Phase detector frequency).

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