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LMK04828BEVM: LMK04828 TICSPRO software configuration

Aleena Jose
Prodigy 80 points
Part Number: LMK04828BEVM
Other Parts Discussed in Thread: LMK04828, LMK04832

Hi,

Is it possible to provide TICSPRO software configuration settings for an application, in which the device gets reference clock 535 MHz on its Clkin1 input and will produce 6 output clocks. Three outputs with frequency 8.359375 MHz, one clock with frequency 66.875MHz and two output clocks with frequency 535 MHz.

Any help will be greatly appreciated.

Thanks.

  • 0
    Prodigy 80 points

    Hi Derek Payne,

    I tried to configure TICS pro for my application but I'm not getting required output.

    "Application, in which the device gets reference clock 535 MHz on its Clkin1 input and will produce 6 output clocks. Three outputs with frequency 8.359375 MHz, one clock with frequency 66.875MHz and two output clocks with frequency 535 MHz."

    Any input on this?

  • 0
    TI__Genius 9920 points

    Limited VCO frequency range, LMK04828 can output 535 MHz.

    Try to use LMK04832 with VCO frequency = 2675 MHz.

  • 0 in reply to Shawn Han
    Prodigy 80 points

    Hi Shawn Han,

    I'm using LMK04828 device for my application. Isn't it possible to get these outputs on LMK04828.

    "

    Three outputs with frequency 8.359375 MHz, one clock with frequency 66.875MHz and two output clocks with frequency 535 MHz.

    "

    Thanks.

  • 0 in reply to Aleena Jose
    TI__Mastermind 28960 points

    Hello Aleena,

    Apologies for the delay. I think we misunderstood and assumed you wanted to use the PLL, instead of operating in distribution mode.

    It is possible to get the three frequencies specified:

    • 535 MHz: Can be achieved either by using Bypass mode on the DCLKoutX_MUX, or by using Divider+DCC+HS mode on the DCLKoutX_MUX and setting the divider to 1. Note that Bypass mode does not allow digital/analog delay or half-step tuning, whereas the Divide-by-1 approach does allow half-step and analog delay. (Digital delay is not usually useful when divide=1, since each digital delay cycle advances the divide-by-1 clock 360° and no real phase change occurs)
    • 66.875MHz: divide by 8
    • 8.359375MHz: use the SYSREF divider and divide by 64. Only odd-numbered outputs (1,3,...,11) can be used for this output, since only odd-numbered outputs are connected to the SYSREF path. Make sure SYSREF_PD=0 and the SYSREF_MUX is set to 0x3 (continuous).

    You can use the "Set Modes" page in TICS Pro to set the LMK04828 to distribution mode. Make sure that FB_MUX_EN=0. I leave it to you to decide which clock outputs should be used. Consider the pinout diagram in datasheet section 6, and try to optimize for crosstalk spurs such that clocks with dissimilar frequencies are in separate clock groups.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 80 points

    Hi Derek,

    I tried the above mentioned configurations.

    I'm able to configure clock outs for 535MHz and 66.875MHz.

    But in the case of 8.359375Mz, with all the seting I'm getting the SYSREF frequency as 8.359375MHz but same is not observed in clock outs. Is there any setting I might be missing?

    Is PLL1 involved in distribution mode?
    Is it possible to get these outputs with PLL1 since I'm giving reference clock 535 MHz on its Clkin1 input.

    Thanks.

  • 0 in reply to Aleena Jose
    TI__Mastermind 28960 points

    Hello Aleena,

    Did you also ensure that the SYSREF path is enabled and routed to the desired output? SDCLKoutY_PD=0, SDCLKoutY_MUX=1 (SYSREF).

    LMK04828 is not able to generate 8.359375MHz on device clocks, because the SYSREF path is not routed to even-numbered outputs. There is only one clock distribution path driving all the device clocks, and the maximum device clock divide value is 31, so it is not possible to generate 8.359375MHz on device clock outputs while simultaneously generating 535MHz on other device clock outputs. In other words, LMK04828 can only generate your 8.359375MHz from SYSREF-capable odd-numbered outputs.

    Neither PLL1 nor PLL2 is involved in distribution mode. While it is technically possible to use only PLL1 on LMK04828, using one or both of the PLLs does not alter the fundamental limitations of the device clock dividers or the output routing.

    LMK04832 is p2p-compatible with LMK04828, the integrated VCO can operate at 3210MHz (535*6), maximum device clock divider value is 1023, and the device clocks and SYSREFs can be routed to any output (odd or even), so you could easily generate 535MHz and 8.359375MHz simultaneously on any output you needed in a number of different ways. If the limitations of the LMK04828 are not acceptable for your application, consider using the LMK04832 instead.

    Regards,

  • 0 in reply to Derek Payne
    Prodigy 80 points

    Hi Derek,

    Thank you for your response. It worked.


    For my another application I require all the clock outs as 80MHz when the reference input is 80MHz in Clkin1.
    I'm getting clockout's as 80MHz when setting the clock divider value as 24.
    Which mode should I set for a proper output.
    I'm getting VCO1 frequency as 1920MHz. Is this fine or which VCO should be selected and what should be the frequency.
    Any other configuration that has to be taken care of.

    Thanks.

  • 0 in reply to Aleena Jose
    TI__Mastermind 28960 points

    Hello Aleena,

    I'm not sure how you're getting the results you describe, as 1920MHz isn't in range for either of the VCOs. I'm also not clear on if you want to use the PLLs and the VCOs, or just distribution mode.

    If you want to use the integrated VCO: the VCO ranges for LMK04828 are 2370 to 2630 MHz (VCO0) and 2920 to 3080 MHz (VCO1) Due to the divider maximum value of 31, the only valid VCO frequencies which can generate 80MHz on LMK04828 are 2400MHz and 2480MHz. You most likely want to use VCO0 at 2400MHz, with an output divide of 30. Note that if you plan to use the internal VCO, you will need to deliver a reference frequency that is an integer divide of 2400MHz to the OSCin pins, as CLKin1 is not connected to PLL2 reference input on LMK04828. If you are required to input 80MHz on CLKin1 and you want to use the internal VCO, you will also need to enable PLL1 and use an external VCXO as the OSCin reference and PLL1 feedback. Possible VCXO frequencies include 80MHz, 100MHz, 50MHz, and anything else that is an integer divide of 2400MHz.

    If your 80MHz clock is good enough as is, and you just need distribution mode, set the device to distribution mode from the `Set Modes` page. You then have two options:

    1. Set DCLKoutX_MUX = 2 (bypass). This will directly buffer CLKin1 to the output format circuit with no analog or digital delay and no divider. However, this is only available on even-numbered outputs (0, 2, ..., 12).
    2. Set DCLKoutX_MUX = 1 (Divider+DCC+HS), and set the divider to 1. This will be slightly higher noise than bypass mode, but it allows all outputs to use the signal from the divide-by-1 (when SDCLKoutY_MUX is set as Device Clock), instead of just even-numbered outputs like in bypass mode.

    Regards,