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TPL5110-Q1: Extended DELAY/M_DRV assertion

Part Number: TPL5110-Q1
Other Parts Discussed in Thread: TPL5110

I'd like to use the TPL5110 in a one shot mode to create a delay between an external switch being pressed and an action being taken in my system.  In the datasheet I noticed the following statement that I would like clarification on:

"An extended assertion of a logic HIGH at the DELAY/M_DRV pin will turn on the MOSFET for a time longer than the programmed time interval. DONE signals received while the DELAY/M_DRV is HIGH are ignored. If the DRV is already LOW (MOSFET ON) the manual power ON is ignored."

How much longer of a time? My external switch is an estop button and will remain asserted, so I'm curious if the DRV pin remains statically low if M_DRV remains asserted?  I need that rising edge on the DRV pin to clock a flop in order to trigger a delayed action from the estop.

Thanks,

Trey

  • Hi Trey,

    While there is a logic HIGH condition at the DELAY/M_DRV pin, the timer's counters are in perpetual reset condition. DELAY/M_DRV falling edge and staying low for tDB (about 20ms) is required for the timer to begin counting the programmed interval.

    It seems like you would be better off using the estop button to connect VDD to the timer in one-shot mode. Per section 7.4.3, Figure 10 suggests the action would be taken immediately after POR + Resistance Reading (tR_EXT). tR_EXT, the time from applying VDD to the DRV pin action, is approximately 100ms (120ms max) per the electrical characteristics. I would also make some time allowance for debouncing, if the estop is expected to have some switch bounce.

    Regards,