Hi Team,
My customer is using LMK05028. We found one unlock issue. The REF input is 10M. And when there is a spur locate at 30.72M and the power is ~-40dBm, the LMK05028 is unlock. When remove the spur, it locked again. We suspect that the device's rejection of the spur is not strong enough. Need to check with you, if there is a way to increase the rejection of the spur's influence at LMK05028 side. Thanks!
Hi,
So the spur observed at an output from the DPLL2/APLL2 loop, causes DPLL2 to be unlocked? This spur is from another device that's on the board. Is this device close to the reference input?
To understand what's causing the DPLL2 to unlock, we need to know a few things, is the reference DPLL2 trying to lock to, valid? Does DPLL2 select that reference? Here's the GUI image where this data can be found, if you hover over it it will also tell you register numbers and bits that correspond to this info:
If the reference is invalid - we'd need to understand what part of the validation checks is causing to become invalid when the spur is there.
If it is valid, the DPLL should be locked unless it's a bad configuration. Which shouldn't be the case since you mentioned if there's no spur the DPLL is locked.
Thanks and regards,
Amin
Hi Amin,
30.72M comes to the device by the REFIN0 and you can find the tcs files as attached.
When there is no spur and input 10M 0dBm reference into REFIN0, the register status is as below:
0x2E6 -- 0x30
0x2FF-- 0x02
0x303--0x01
DPLL2 loss of lock: 0 DPLL2 lock
DPLL2 REF0 selected ： 1 selected
When there is 30.72M spur and input 10M 0dBm reference into REFIN0, the register status is as below:
0x2E6 -- 0x20
0x2FF-- 0x02
0x303--0x00
DPLL2 loss of lock: 1 DPLL2 unlock
DPLL2 REF0 selected ： 0
After removing the 30.72 spur, the register status change to the status in the 1st step(no spur status).
Hello,
Thank you for the information and sharing the .tcs file. So when the spur is there, it's IN0 is no longer valid.
I noticed in your .tcs file that IN0 can support either DPLL1 or DPLL2 based off of inputs however for DPLL reference selection only IN0 has a priority. If this is changed, the DPLL2 can lock to IN1 as well. How to update the priority selection in the GUI with image at the bottom of the email.
The question of why IN0 becomes invalid and IN1 remains valid is understood now as well. IN0 has PPM detector enabled. Not sure what the requirements for the system are... but you can disable IN0 PPM detector or at least increase the invalid threshold. The spur is causing enough noise where this is becoming invalid.
On a similar note, I would advise that missing clock is enabled - there's no harm in this and it would allow DPLL to realize a loss of reference much faster and enter holdover before corruption or large frequency error can occur.
Thanks and regards,
Amin
DPLL2 Auto Priority change:
PPM detect and missing (late/early) clock detect
Hi Amin,
1. LMK05028 IN0 from EXT 10MHz input，lmk05028 IN1 from lmk05028 out0 10MHz 1/2 Vpp, so we can just check DPLL2 IN0.
2. You can find the tcs file as attached (lmk05028 BTS 10Hz fae 1016)
disable Valid IN0,
Enable missing clock (when late clocks =0, input check is valid, so set it to 1 )
Enable runt pulse
3. When there is no spur and input 10M 0dBm reference into REFIN0, the register status is as below:
0x2E6 -- 0x30
0x2FF-- 0x02
0x303--0x01
DPLL2 loss of lock: 0 DPLL2 lock
DPLL2 REF0 selected ： 1 selected
4. When there is 30.72M spur, reg is as below(no change of the reg,DPLL2 unlock):
0x2E6 --0x30
0x2FF-- 0x02
0x303--0x01
DPLL2 loss of lock: 1 DPLL2 unlock
DPLL2 REF0 selected ： 1 selected
When switch off the spur, the reg recover to the status when there is no spur
5. When enable missing clock late clocks=0, and 10M 0dBm ref input to refin0 and no spur:
0x2E6 -- 0x20
0x2FF-- 0x02
0x303--0x00
DPLL2 loss of lock: 0 DPLL2 lock
DPLL2 REF0 selected ： 0
Hi Amin,
1，Spur comes from IN0, is not comes from OUT0,Spur added DPLL2 unlock，DPLL1 lock
2,
1) OUT0 no spur: DPLL2 is locked to IN0, DPLL1 locks to IN1 which is fed back from OUT0
—— IN0 no spur: DPLL2 is locked to IN0, DPLL1 locks to IN1 which is fed back from OUT0
2) OUT0 has spur: DPLL2 doesn't lock to IN0 (even though it should be unimpacted) DPLL1 locks to IN1 (even though this has the spur coming from Output0?)
—— IN0 has spur: DPLL2 doesn't lock to IN0( this has the spur) ,DPLL1 locks to IN1
