Other Parts Discussed in Thread: LMX2594, LMX2572, LMX2572LP, TICSPRO-SW
I'm using LMX2571 as a carrier recovery stage - 49.92 MHz CW in at ref input, and 38.6 MHz out. It's running ok but occasionally there's a brief drop - in ms - in 49.92 input level. The PLL output suddenly shows a 180 degree phase shift (lock detect stays 'on'). I understand this PLL uses a phase-frequency detector so that should not be a problem. Is it possible that one of the input multiplier/divider stages re-starts at the opposite phase (both dividers at 1, multiplier at 2) or is there some other phase ambiguity stage in the PLL? Obviously I'm going to stabilize the input level but it would be useful to know what the underlying PLL characteristic is.
Thank you